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In general a given reference design of an FMC board is deployed to just a few carrier, although several FPGA board is supported in ADI's HDL repository. The simple reason behind this practice is that, it would create a tremendous maintenance workload, that would require a lot of human resources, and would increase the required time for testing. The general rule of thumb is to support a given project with a fairly popular carrier (e.g. ZC706 or A10SoC), which is powerful enough to showcase the board features and maximum performance. All the HDL projects were designed to maximize source code reuse, minimize maintainability and ease portability. The result of these design goals is that porting a given project to another carrier is fairly simple, if the user respects a couple of guide lines. The main scope of this wiki page is to discuss this guide line and provide simple indications for users who wants to port a project to a non-supported carrier.
There are two type of FMC connector : LPC (Low Pin Count) and HPC (High Pin Count). In general an FMC board is using an FMC connector type, which has enough pins for the required interfaces between the IO devices and FPGA. A carrier with an FMC HPC connector can host FMC board with an LPC or HPC connector, but a carrier with an FMC LPC can host a board just with an FMC LPC connector.
The most important things to check before porting, which are related to the ANSI/VITA 57.1 standard (list is not necessarily exhaustive):
At HDL Architecture wiki describes a generic base design and possible components of it. User should look at it as a suggestion only.
To create a new base design for a given Xilinx FPGA carrier board, the following steps should be taken (the zcu102 carrier was used as example).
First, you need to create a new directory in ~/projects/common with the name of the carrier.
[~/hdl]cd projects/common [~/hdl]mkdir zcu102
The following files should be created or copied into the directory:
You should define the board and its device in the flow script (adi_project.tcl), by adding the following lines to the beginning of the adi_project_create process:
if [regexp "_zcu102$" $project_name] { set p_device "xczu9eg-ffvb1156-1-i-es1" set p_board "xilinx.com:zcu102:part0:1.2" set sys_zynq 2 }
The sys_zynq constant variable should be set in the following way:
To create a new base design for a given Intel FPGA carrier board, the following steps should be taken (the zcu102 carrier was used as example).
The following files should be created or copied into the directory:
You should define the board and its device in the flow script (adi_project_alt.tcl), by adding the following lines to the beginning of the adi_project_altera process:
if [regexp "_a10soc$" $project_name] { set family "Arria 10" set device 10AS066N3F40E2SG set system_qip_file system_bd/system_bd.qip }
To follow the project framework as much as possible, the easiest way is to copy all the projects file from an already existing project, and modifying those file to support the new carrier. A project for a Xilinx FPGA board should contain the following files:
To follow the project framework as much as possible, the easiest way is to copy all the projects file from an already existing project, and modifying those file to support the new carrier. A project for an Intel FPGA board should contain the following files:
You can ask question at FPGA Reference Design EZ community.
Threads that discuss this issue: