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resources:fpga:docs:hdl:porting_project_quick_start_guide [02 Feb 2018 15:13]
AdrianC Wording changes
resources:fpga:docs:hdl:porting_project_quick_start_guide [21 Mar 2018 13:55]
CsomI The example with a Xilinx standalone project is redundant
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 ==== Example with a Xilinx board ==== ==== Example with a Xilinx board ====
  
-In this section we are presenting all the necessary steps to create a base design for the Xilinx ZCU102 development board.+In this sectionwe are presenting all the necessary steps to create a base design for the Xilinx ZCU102 development board.
  
 First, you need to create a new directory in ~/​projects/​common with the name of the carrier. First, you need to create a new directory in ~/​projects/​common with the name of the carrier.
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   * **system_constr.xdc** - Constraint files of the board design. Here is defined the FMC IO's and board specific clock signals. All the IO definition must be updated, with the new pin names.   * **system_constr.xdc** - Constraint files of the board design. Here is defined the FMC IO's and board specific clock signals. All the IO definition must be updated, with the new pin names.
   ​   ​
-  * **system_top.v** - Top wrapper file, in which the system_wrapper.v module is instantiated,​ and a few I/O macros are defined. The IO port of this verilog ​module will be connected to actual IO pads of the FPGA. The simplest way to update the system_top is to let the synthesis fail and the tool will tell which ports are missing or which ports are redundant. The first thing to do after the failure is to verify the instantiation of the system_wrapper.v. This file is a tool generated file and can be found at <​project_name>​.srcs/​sources_1/​bd/​system/​hdl/​system_wrapper.v. Fixing the instantiation of the wrapper module in most cases eliminates all the errors. If you get errors that you can not fix, ask for support.+  * **system_top.v** - Top wrapper file, in which the system_wrapper.v module is instantiated,​ and a few I/O macros are defined. The IO port of this Verilog ​module will be connected to actual IO pads of the FPGA. The simplest way to update the system_top is to let the synthesis fail and the tool will tell which ports are missing or which ports are redundant. The first thing to do after the failure is to verify the instantiation of the system_wrapper.v. This file is a tool generated file and can be found at <​project_name>​.srcs/​sources_1/​bd/​system/​hdl/​system_wrapper.v. Fixing the instantiation of the wrapper module in most cases eliminates all the errors. If you get errors that you can not fix, ask for support.
  
   * **Makefile** - This is an auto-generated file, but after updating the carrier name, should work with the new project without an issue.   * **Makefile** - This is an auto-generated file, but after updating the carrier name, should work with the new project without an issue.
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   * **system_constr.sdc** - Contains clock definitions and other path constraints   * **system_constr.sdc** - Contains clock definitions and other path constraints
  
-  * **system_top.v** - Top wrapper file of the project. The IO port of this verilog ​module will be actual IO pads of the FPGA. Need to make sure that the base design'​s IOs are updated. (Delete nonexistent IO or add new ones). The simplest way to update the system_top is to let the synthesis fail and the tool will tell which ports are missing or which ports are redundant.+  * **system_top.v** - Top wrapper file of the project. The IO port of this Verilog ​module will be actual IO pads of the FPGA. Need to make sure that the base design'​s IOs are updated. (Delete nonexistent IO or add new ones). The simplest way to update the system_top is to let the synthesis fail and the tool will tell which ports are missing or which ports are redundant.
  
   * **Makefile** - This is an auto-generated file, but after updating the carrier name, it should work with the new project without an issue.   * **Makefile** - This is an auto-generated file, but after updating the carrier name, it should work with the new project without an issue.
resources/fpga/docs/hdl/porting_project_quick_start_guide.txt · Last modified: 21 Aug 2019 17:47 by SPop612