Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision | |||
|
resources:fpga:docs:hdl:m2k [17 Dec 2019 13:37] Stanca-Florina Pop Update block diagram |
resources:fpga:docs:hdl:m2k [14 Jan 2021 05:24] Robin Getz use / interwiki links |
||
|---|---|---|---|
| Line 45: | Line 45: | ||
| The TX (DAC) interface works at 75MSPS data rate with interpolation by 2 on the AD9963 chip. The DAC path inside AD9963 chip works at 150MHz, pushing part of the spurs outside the 100MHz bandwidth. Given that the reference clock for AD9963 is 100 MHz and DACs maximum sampling rate is 170 MSPS, this is the best option available. The 75MHz clock is not available in the FPGA. In order to reduce the number of PLL used in the FPGA, we are using AD9963 and a BUFR (divide by 2) to generate this clock. When the clock is generated by AD9963, DDR transfer is not available. The TX interface works at 150 MHz, SDR. The IO standard is CMOS at 3.3V. \\ | The TX (DAC) interface works at 75MSPS data rate with interpolation by 2 on the AD9963 chip. The DAC path inside AD9963 chip works at 150MHz, pushing part of the spurs outside the 100MHz bandwidth. Given that the reference clock for AD9963 is 100 MHz and DACs maximum sampling rate is 170 MSPS, this is the best option available. The 75MHz clock is not available in the FPGA. In order to reduce the number of PLL used in the FPGA, we are using AD9963 and a BUFR (divide by 2) to generate this clock. When the clock is generated by AD9963, DDR transfer is not available. The TX interface works at 150 MHz, SDR. The IO standard is CMOS at 3.3V. \\ | ||
| - | More information: [[ https://wiki.analog.com/resources/fpga/docs/axi_ad9963 | AXI AD9963 documentation ]] | + | More information: [[/resources/fpga/docs/axi_ad9963 | AXI AD9963 documentation ]] |
| ==== AXI_ADC_TRIGGER ==== | ==== AXI_ADC_TRIGGER ==== | ||
| Line 62: | Line 62: | ||
| The output of the core embeds the triggers in the data words, as only 12 bits of the 16 bit word are used for data. These need to be extracted before being forwarded to the DMA. Embedding the trigger with the data allows for additional IPs with unknown pipeline length to be introduced in the path. \\ | The output of the core embeds the triggers in the data words, as only 12 bits of the 16 bit word are used for data. These need to be extracted before being forwarded to the DMA. Embedding the trigger with the data allows for additional IPs with unknown pipeline length to be introduced in the path. \\ | ||
| - | More information: [[ https://wiki.analog.com/resources/fpga/docs/axi_adc_trigger | AXI ADC TRIGGER documentation ]] | + | More information: [[/resources/fpga/docs/axi_adc_trigger | AXI ADC TRIGGER documentation ]] |
| ==== UTIL_VAR_FIFO ==== | ==== UTIL_VAR_FIFO ==== | ||
| Line 68: | Line 68: | ||
| The UTIL_VAR_FIFO IP allows M2K to store and display data before the trigger. In the design, it has a length of 8192 and can easily be increased. The IP controls an external BRAM. If DEPTH is 0, the FIFO is bypassed. When the DEPTH is changed, the read and write pointers are reset, effectively resetting the FIFO. There is a 2 cycle clock latency, even if it’s bypassed. If valid is not always asserted (decimation is active), the latency is 1 clock cycle instead of two. | The UTIL_VAR_FIFO IP allows M2K to store and display data before the trigger. In the design, it has a length of 8192 and can easily be increased. The IP controls an external BRAM. If DEPTH is 0, the FIFO is bypassed. When the DEPTH is changed, the read and write pointers are reset, effectively resetting the FIFO. There is a 2 cycle clock latency, even if it’s bypassed. If valid is not always asserted (decimation is active), the latency is 1 clock cycle instead of two. | ||
| - | More information: [[ https://wiki.analog.com/resources/fpga/docs/util_var_fifo | UTIL VARIABLE FIFO documentation ]] | + | More information: [[/resources/fpga/docs/util_var_fifo | UTIL VARIABLE FIFO documentation ]] |
| ==== UTIL_EXTRACT ==== | ==== UTIL_EXTRACT ==== | ||
| Line 74: | Line 74: | ||
| The UTIL_EXTRACT IP will extract the trigger that was embedded in the data stream by the AXI_ADC_TRIGGER IP. | The UTIL_EXTRACT IP will extract the trigger that was embedded in the data stream by the AXI_ADC_TRIGGER IP. | ||
| - | More information: [[ https://wiki.analog.com/resources/fpga/docs/util_extract | UTIL EXTRACT documentation ]] | + | More information: [[/resources/fpga/docs/util_extract | UTIL EXTRACT documentation ]] |
| ==== AXI_ADC_DECIMATE ==== | ==== AXI_ADC_DECIMATE ==== | ||
| Line 84: | Line 84: | ||
| At the end of the filter chain, there is an arbitrary decimation block. The arbitrary decimation can be activated independently and it does not implement any type of filtering. \\ | At the end of the filter chain, there is an arbitrary decimation block. The arbitrary decimation can be activated independently and it does not implement any type of filtering. \\ | ||
| - | More information: [[ https://wiki.analog.com/resources/fpga/docs/axi_adc_decimate | AXI ADC DECIMATE documentation ]] | + | More information: [[/resources/fpga/docs/axi_adc_decimate | AXI ADC DECIMATE documentation ]] |
| ==== AXI_DAC_INTERPOLATE ==== | ==== AXI_DAC_INTERPOLATE ==== | ||
| Line 94: | Line 94: | ||
| At the end of the filter blocks, we have an arbitrary interpolation zero-order hold block which holds the value for a configurable number of samples. \\ | At the end of the filter blocks, we have an arbitrary interpolation zero-order hold block which holds the value for a configurable number of samples. \\ | ||
| - | More information: [[ https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate | AXI DAC INTERPOLATION documentation ]] | + | More information: [[/resources/fpga/docs/axi_dac_interpolate | AXI DAC INTERPOLATION documentation ]] |
| ==== AXI_LOGIC_ANALYZER ==== | ==== AXI_LOGIC_ANALYZER ==== | ||
| Line 111: | Line 111: | ||
| If the FIFO is active, it is filled before being read, not forwarding any data until it is full. The maximum size of the FIFO is 8192 samples. The FIFO is implemented using BRAM blocks configured for minimal power consumption. \\ | If the FIFO is active, it is filled before being read, not forwarding any data until it is full. The maximum size of the FIFO is 8192 samples. The FIFO is implemented using BRAM blocks configured for minimal power consumption. \\ | ||
| - | More information: [[ https://wiki.analog.com/resources/fpga/docs/axi_logic_analyzer | AXI LOGIC ANALYZER documentation ]] | + | More information: [[/resources/fpga/docs/axi_logic_analyzer | AXI LOGIC ANALYZER documentation ]] |
| ==== Pinout Table ==== | ==== Pinout Table ==== | ||
resources/fpga/docs/hdl/m2k.txt · Last modified: 14 Jan 2021 05:24 by Robin Getz