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resources:fpga:docs:hdl:generic_jesd_bds [14 Jan 2021 05:24] Robin Getz use ez> / interwiki links |
resources:fpga:docs:hdl:generic_jesd_bds [20 Sep 2021 09:56] Laszlo Nagy replace DPW with SPC |
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| ===== Generic Tx path ===== | ===== Generic Tx path ===== | ||
| - | The below diagram presents a generic JESD Tx path from application layer to the FPGA boundary. The application layer is connected to the Tx path through the DAC Transport Layer which for each converter accepts a data beat on every cycle. The width of data beat is defined by the DPW (data path width) and NP parameter. DPW represents the number of samples per converter per data clock cycle. DPW must be a natural number (greater than one and a whole number). | + | The below diagram presents a generic JESD Tx path from application layer to the FPGA boundary. The application layer is connected to the Tx path through the DAC Transport Layer which for each converter accepts a data beat on every cycle. The width of data beat is defined by the SPC and NP parameter. SPC represents the number of samples per converter per data clock cycle. SPC must be a natural number (greater than one and a whole number). |
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| On each clock cycle the Link Layer accepts 32 bits per every lane as a constraint from the physical layer that is configured to 32bit mode. This means that for each clock cycle the application layer must provide enough samples for each converter so the transport layer can fill 32 bits of data for each lane. Due this constraint the following equation must hold: | On each clock cycle the Link Layer accepts 32 bits per every lane as a constraint from the physical layer that is configured to 32bit mode. This means that for each clock cycle the application layer must provide enough samples for each converter so the transport layer can fill 32 bits of data for each lane. Due this constraint the following equation must hold: | ||
| - | <m> L*32 = M*NP*DPW </m> | + | <m> L*32 = M*NP*SPC </m> |
| In such design the following constraints apply to the transport layer: | In such design the following constraints apply to the transport layer: | ||
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| In this mode the Transport Layer will output two frames in every clock cycle. 32 bits / (F*8) = 2; \\ | In this mode the Transport Layer will output two frames in every clock cycle. 32 bits / (F*8) = 2; \\ | ||
| The application layer must provide 8 samples each cycle to be able to fill the 2 frames. | The application layer must provide 8 samples each cycle to be able to fill the 2 frames. | ||
| - | DPW = (L*32) / (M*NP) = (4*32) / (1*16) = 128/16 = 8 | + | SPC = (L*32) / (M*NP) = (4*32) / (1*16) = 128/16 = 8 |
| {{ :resources:fpga:docs:hdl:sample_tx_jesd_path.png?direct&600 |}} | {{ :resources:fpga:docs:hdl:sample_tx_jesd_path.png?direct&600 |}} | ||
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| In this mode the Transport Layer will output two frames in every clock cycle. 32 bits / (F*8) = 2; \\ | In this mode the Transport Layer will output two frames in every clock cycle. 32 bits / (F*8) = 2; \\ | ||
| The application layer must provide 8 samples each cycle to be able to fill the 2 frames. | The application layer must provide 8 samples each cycle to be able to fill the 2 frames. | ||
| - | DPW = (L*32) / (M*NP) = (4*32) / (4*16) = 128/64 = 2 | + | SPC = (L*32) / (M*NP) = (4*32) / (4*16) = 128/64 = 2 |
| {{ :resources:fpga:docs:hdl:generig_jesd_tx_samples_ex2.png?direct&600 |}} | {{ :resources:fpga:docs:hdl:generig_jesd_tx_samples_ex2.png?direct&600 |}} | ||
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| ===== Generic Rx path ===== | ===== Generic Rx path ===== | ||
| - | The below diagram presents a generic JESD Rx path. The application layer is connected to the Rx path through the ADC Transport Layer which for each converter generates a data beat on every cycle. The width of data beat is defined by the DPW (data path width) and NP parameter. DPW represents the number of samples per converter per data clock cycle. DPW must be a natural number (greater than one and a whole number). | + | The below diagram presents a generic JESD Rx path. The application layer is connected to the Rx path through the ADC Transport Layer which for each converter generates a data beat on every cycle. The width of data beat is defined by the SPC and NP parameter. SPC represents the number of samples per converter per data clock cycle. SPC must be a natural number (greater than one and a whole number). |
| {{ :resources:fpga:docs:hdl:generic_rx_jesd_path.png?direct&600 |}} | {{ :resources:fpga:docs:hdl:generic_rx_jesd_path.png?direct&600 |}} | ||
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| In this mode the Transport Layer will accept two frames in every clock cycle. 32 bits / (F*8) = 2; \\ | In this mode the Transport Layer will accept two frames in every clock cycle. 32 bits / (F*8) = 2; \\ | ||
| The application layer must accept 8 samples each cycle so the transport layer can deframe the 2 frames. | The application layer must accept 8 samples each cycle so the transport layer can deframe the 2 frames. | ||
| - | DPW = (L*32) / (M*NP) = (4*32) / (1*16) = 128/16 = 8 | + | SPC = (L*32) / (M*NP) = (4*32) / (1*16) = 128/16 = 8 |
| {{ :resources:fpga:docs:hdl:sample_rx_jesd_path.png?direct&600 |}} | {{ :resources:fpga:docs:hdl:sample_rx_jesd_path.png?direct&600 |}} | ||
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| ===== Support ===== | ===== Support ===== | ||
| Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[ez>community/fpga|EngineerZone]]. | Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[ez>community/fpga|EngineerZone]]. | ||
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resources/fpga/docs/hdl/generic_jesd_bds.txt · Last modified: 20 Sep 2021 09:56 by Laszlo Nagy