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resources:fpga:docs:hdl:fmcomms2_fir_filt [19 May 2017 17:22] – Update Andrei Grozavresources:fpga:docs:hdl:fmcomms2_fir_filt [14 Jan 2021 05:24] (current) – use / interwiki links Robin Getz
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-===== Adding FIR filters in a fmcomms2 design =====+===== Integrate FIR filters into the FMCOMMS2 HDL design =====
  
-This document contains details of how can one add simple signal processing blocks (digital filters) in the ADI HDL reference design. We have frequent questions on how a custom IP can be integrated in the reference design, or where to place it in the signal path. This tutorial tries to answer those questions.+This wiki page describes how to add a custom processing module into the FMCOMMS2's TX and/or RX data path. In this example, the custom modules are going to be some digital FIR filters, to decimate and interpolate the incoming and outcoming data stream.  
  
-Let’s presume we want to transmit a sinewave with the AD9361 ADI Integrated RF transceiver, the sinewave frequency is below 6 MHz, for this we can use a lower system data rate than the reference design. But, by simply lowering the data rate of the system we will increase the equalization error. To avoid this inconvenience we can add some interpolation filters for transmit. A similar problem is encountered on the ADC side when receiving a low frequency signal. This can be solved with the use of decimation filters. In our example these filters where already implemented in “util_fir_int” and “util_fir_dect” HDL IP core, which are wrappers for the FIR Compiler Xilinx IP. The wrappers are used to manage the data rates entering the filter and for the ease of setting the filter parameters for a specific application (Tx/Rx).+<note important> 
 +This example was build using  
 +[[ https://github.com/analogdevicesinc/hdl/releases/tag/eg_fmcomms2_fir_filter|fmcomms2_fir_filters ]] GitHub HDL branch, using Vivado 16.2 and 16.4 versions. 
 +</note> 
 + 
 +Let’s presume we want to transmit a sinewave with the AD9361 ADI Integrated RF transceiver, the sinewave frequency is below 6 MHz, for this, we can use a lower system data rate than the reference design. But, by simply lowering the data rate of the system we will increase the equalization error. To avoid this issue we can add some interpolation filters for transmitting. A similar problem is encountered on the ADC side when receiving a low-frequency signal. This can be solved with the use of decimation filters. In our example, these filters were already implemented in “util_fir_int” and “util_fir_dect” HDL IP core, which are wrappers for the FIR Compiler Xilinx IP. The wrappers are used to manage the data rates entering the filter and to facilitate the configuration of the filter parameters for a specific application (Tx/Rx).
  
 === Choosing filter parameters and coefficients === === Choosing filter parameters and coefficients ===
-The interpolation/decimation filters parameters and coefficients where chosen/calculated in MatLab.+The interpolation/decimation filters parameters and coefficients were calculated in MatLab.
  
 Interpolation FIR filter: Interpolation FIR filter:
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 === Adding the filters in the data path === === Adding the filters in the data path ===
  
-In the original fmcomms2 design the data comes from the DMA, goes to util_unpack core which transmits the individual channel data to a dac_fifo core, from which the ad9361 core reads the data and transmits it to the AD9361 CHIP. +In the original fmcomms2 design the data comes from the DMA, goes to the util_upack core which transmits the individual channel data to a dac_fifo core, from which the ad9361 core reads the data and transmits it to the AD9361 CHIP. 
-util_unpack core is used to split the 64 bit data containing 2 RF channels, each one having I/Q data. +The util_upack core is used to split the 64-bit data containing 2 RF channels, each one having I/Q data. 
-dac_fifo is used for the clock crossing between the system clock and the AD9361 clock.+dac_fifo is used for clock domain crossing between the system clock and the AD9361 clock.
  
-The FIR filter works best at low clock frequencies. This is the reason for placing it in front of the dac_fifo module.  The required input data for the filter is I/Q data and the output is independent I and Q data. Because of this conditions, we still require the upack module, but we only need to split the dac data into independent channel data, so we need one unpack module and two util_fir_int modules before the fifo.+The data processing is done at lower clock frequencies. This is the reason for placing the interpolation filters in front of the dac_fifo module.  The required input data for the filter is I/Q data and the output is independent I and Q data. Because of this conditions, we still require the util_upack module, but we only need to split the DAC data into independent channel data, so we need one unpack module and two util_fir_int modules before the FIFO.
 The same approach is implemented on the receive path. The same approach is implemented on the receive path.
 For more information about the reference design visit: For more information about the reference design visit:
-  * [[https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz |fmcomms2 user guide]] +  * [[/resources/eval/user-guides/ad-fmcomms2-ebz |fmcomms2 user guide]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/hdl| HDL user guide]]+  * [[/resources/fpga/docs/hdl| HDL user guide]]
  
 The modified reference design block diagram containing now Interpolation and Decimation filters is presented below. The modified reference design block diagram containing now Interpolation and Decimation filters is presented below.
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 ==== Adding FIR filters in fmcomms2 design and building the HDL ==== ==== Adding FIR filters in fmcomms2 design and building the HDL ====
  
-In order to use the ADI frame work, one needs to set an environment variable pointing to the ADI HDL folder and source the TCL procedures. +The design is obtain by simply sourcing the base fmcomms2 block design.
-<code php> +
-set ad_hdl_dir $::env(ADI_HDL_DIR) +
-set ad_phdl_dir $ad_hdl_dir  +
- +
-source $ad_hdl_dir/projects/scripts/adi_board.tcl +
-source $ad_hdl_dir/projects/scripts/adi_project.tcl +
-</code> +
-  +
-Then we set the “zynq” flag and create the new project. Set the board part for the desired settings.+
  
 <code php> <code php>
-set sys_zynq 1 +set project_dir [pwd] 
-create_project zc706 . -part xc7z045ffg900-2 -force +cd $ad_hdl_dir/projects/fmcomms2/zc706/ 
-set_property board_part xilinx.com:zc706:part0:1.2 [current_project]+source system_bd.tcl 
 +cd $project_dir
 </code> </code>
  
-The board design is inherited by simply sourcing the carrier (zc706) and the FMC (fmcomms2) board. +At this point fmcomms2 reference design's TX data path has the following components:
- +
-<code php> +
-create_bd_design "system" +
-source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +
-source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl +
-</code> +
-At this point imported the fmcomms2 reference design which has the following connections for the Tx data path:+
  
 {{:resources:fpga:docs:hdl:fmcomms2_vivado_ref_tx.png?800|}} {{:resources:fpga:docs:hdl:fmcomms2_vivado_ref_tx.png?800|}}
  
-We need to remove the connections between util_upack and dac_fifo cores in order to add the FIR filter modules in the reference design. With the following steps some of the fmcomms2 reference design commands will be overwritten/ignored.+We need to remove the connections between util_upack and dac_fifo cores in order to add the FIR filter modules in the reference design. With the following commands, all the unwanted connections will be removed and new ones will be created.
  
 <code php> <code php>
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 </code> </code>
  
-The interpolation filter has a 32bit(I+Q) input data bus. In the base design the upack module is configured to output 4 channel of 16 bit width. By just by changing the upack number of channels to 2 and width of the channel to 32 bit will not work because of how the independent I/Q channel data is arranged in the 64 bit data bus coming from the DMA see the figure below.+The interpolation filter has a 32-bit (I+Q) input data bus. In the base design, the unpack module is configured to output 4 channels of 16-bit data. By changing the unpack number of channels to 2 and the width of the channels to 32-bit will not work because of how the independent I/Q channel data is arranged in the 64-bit data bus coming from the DMA see the figure below.
  
 {{ :resources:fpga:docs:hdl:ad9361_dma_data.png?nolink |}} {{ :resources:fpga:docs:hdl:ad9361_dma_data.png?nolink |}}
  
-More information about the util_upack_core [[https://wiki.analog.com/resources/fpga/docs/util_upack |util_upack_core]]+More information about the util_upack_core [[/resources/fpga/docs/util_upack |util_upack_core]]
  
 As a fact the data transmuted/received trough LVDS interface at DDR (Double Data Rate) is presented in the diagram below. As a fact the data transmuted/received trough LVDS interface at DDR (Double Data Rate) is presented in the diagram below.
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 At this point we have two options: At this point we have two options:
-- delete the upack_core and split the data with some simple slices +  - delete the upack_core and split the data into some simple slices 
-- keep upack_core and the possibility to use half of the DMA bandwidth when one channel in not enabled. +  - keep upack_core and the possibility to use half of the DMA bandwidth when one channel is not enabled. 
-For this example the upack_core was kept. pack_core proprieties remains unchanged, we need to add concatenate the channel data outputted by upack and send it to each channel interpolate filter.+For this example, the upack_core was kept. The core's proprieties remain unchanged, and a concatenate module was added, in order to merge the data coming out from the unpack module, then feed it into the interpolation filter.
    
 Adding concatenation modules. Adding concatenation modules.
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 </code> </code>
  
-The same principle is applied on the RX path for the pack_core. The difference is that we need to split the data outputted by the decimation filters to obtain the independent I/Q channel data.+The same principle is applied to the RX path for the pack_core. The difference is that we need to split the data outputted by the decimation filters to obtain the independent I/Q channel data.
  
 <code php> <code php>
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 </code> </code>
  
-In this example the TX data flow is controlled by the interpolation filter when interpolation is activated and by the axi_ad9361_core when interpolation is not active. In the reference design the data flow is controlled by the ad9631_core.+In this example, the TX data flow is controlled by the interpolation filter when interpolation is activated and by the axi_ad9361_core when interpolation is not active. In the reference design, the data flow is controlled by the ad9631_core.
  
-We must connect the umpack_core dma_xfer_in port to VCC so that the upack may transmit the valid and enable signals from one entity to another.+We must connect the unpack core's dma_xfer_in port to VCC so that the unpack may transmit the valid and enable signals from one entity to another.
  
 <code php> <code php>
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 </code> </code>
  
-At this moment the Interpolation filters are completely integrated in the design and the data path should look like the one in figure below.+At this moment the Interpolation filters are completely integrated into the design and the data path should look like the one in the figure below.
  
 {{:resources:fpga:docs:hdl:fmcomms2_vivado_interp_fir_tx.png?800|}} {{:resources:fpga:docs:hdl:fmcomms2_vivado_interp_fir_tx.png?800|}}
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 ad_connect fir_decimator_1/decimate decim_slice/Dout ad_connect fir_decimator_1/decimate decim_slice/Dout
 </code> </code>
 +
 +==== Generating the programing files ====
 +
 +Depending if you did your changes in GUI, you can click on "Generate Bitstream". After the bitstream generation is complete. Click on Files > Export > Export Hardware, select include bitstream option.
 +
 +If you did your changes directly in the Tcl files, you can use "make" to generate the bitstream and hdf file.
 +
 +Now depending if your system is based on a zynq architecture, you will have to generate the BOOT.BIN. If you have a MicroBlaze soft processor in your system booting the Linux will is simpler.
 +
 +More info on:
 +  * [[/resources/fpga/docs/build | Building the ADI HDL]]
 +  * [[/resources/tools-software/linux-drivers-all | Building the ADI Linux]]
 +
  
 ==== Base system functionality ==== ==== Base system functionality ====
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 {{ :resources:fpga:docs:hdl:fmcomms2_txrx_loopback.jpg?nolink&500 |}} {{ :resources:fpga:docs:hdl:fmcomms2_txrx_loopback.jpg?nolink&500 |}}
  
-When first booting up the design non of the filters will be active.+When first booting up the design none of the filters will be active.
 For the beginning make sure you have the same LO frequency for RX and TX, as in the picture below. For the beginning make sure you have the same LO frequency for RX and TX, as in the picture below.
-Configure the Transmit/DDS mode to DAC Buffer Output, and chose one of the .mat files there and press Load this will send data in the .mat file via DMA. This option was chosen because the DDS data dose not pass trough the FIR interpolation filters. On the decimation side data will always pass trough decimation filters.+Configure the Transmit/DDS mode to DAC Buffer Output, and chose one of the .mat files there and press Load this will send data in the .mat file via DMA. This option was chosen because the DDS data does not pass through the FIR interpolation filters. On the decimation side, data will always pass through decimation filters.
  
-Below you can see the setting for fmcomms2 and the data plot in FFT and Time Domain for the "sinewave_0.6.mat". As a functionality example only one of the 2 channels will bee enabled.+Below you can see the setting for fmcomms2 and the data plot in FFT and Time Domain for the "sinewave_0.6.mat". As a functionality example, only one of the 2 channels will be enabled.
  
 FFT Domain FFT Domain
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 {{ :resources:fpga:docs:hdl:fmcomms2_fir_setup_activate_dma_data_waveform.png?nolink |}} {{ :resources:fpga:docs:hdl:fmcomms2_fir_setup_activate_dma_data_waveform.png?nolink |}}
  
-To better understand what is happening with the data inside the FPGA, 3 ILA (integrated logic analyzer) modules where added to the HDL design.+To better understand what is happening with the data inside the FPGA, 3 ILA (integrated logic analyzer) modules were added to the HDL design.
 The first ILA was connected to the control signals between the ad9361_core and the dac_fifo. Second ILA is monitoring the interpolation filters and the third ILA the decimation filters. The first ILA was connected to the control signals between the ad9361_core and the dac_fifo. Second ILA is monitoring the interpolation filters and the third ILA the decimation filters.
 As previously discussed above none of the filters are active and only one of the channels is enabled at this point. As previously discussed above none of the filters are active and only one of the channels is enabled at this point.
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 === Interpolation filter === === Interpolation filter ===
  
-In the ** Connecting the FIR interpolation filters on the Tx side** section above, we added a gpio control. +In the ** Connecting the FIR interpolation filters on the Tx side** section above, we added a GPIO control. 
-The ad9361_core gpio control register can be found in the register map at the address 0xBC +The ad9361_core GPIO control register can be found in the register map at the address 0xBC 
 [[resources:fpga:docs:axi_ad9361 |axi_ad9361_core]] [[resources:fpga:docs:axi_ad9361 |axi_ad9361_core]]
  
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 {{ :resources:fpga:docs:hdl:fmcomms2_fir_tx_active_fft.png?nolink |}} {{ :resources:fpga:docs:hdl:fmcomms2_fir_tx_active_fft.png?nolink |}}
  
-The data captured by the ILA conected to the interpolation filters shows the smaller frequency sine wave and the 1/8 valid/clock signals.+The data captured by the ILA connected to the interpolation filters shows the smaller frequency sine wave and the 1/8 valid/clock signals.
 {{ :resources:fpga:docs:hdl:fir_active_interpolators_all_ch_active.png?nolink |}} {{ :resources:fpga:docs:hdl:fir_active_interpolators_all_ch_active.png?nolink |}}
  
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 At this point again all filters are disabled. At this point again all filters are disabled.
  
-Similar with interpolation, to activate the decimation we must go top the Debug, but this time select the "cf-ad9361-lpc". Select the "Register Map Settings" source to be "AXI_CORE" and at the same address 0xBC [[resources:fpga:docs:axi_ad9361 |(axi_ad9361_core)]] this time being the ADC side gpio, write 0x1, as in the example below.+Similar to interpolation, to activate the decimation we must go to the Debug, but this time select the "cf-ad9361-lpc". Select the "Register Map Settings" source to be "AXI_CORE" and at the same address 0xBC [[resources:fpga:docs:axi_ad9361 |(axi_ad9361_core)]] this time being the ADC side GPIO, write 0x1, as in the example below.
  
 {{ :resources:fpga:docs:hdl:activate_rx_interpolation_filters_write.png?nolink |}} {{ :resources:fpga:docs:hdl:activate_rx_interpolation_filters_write.png?nolink |}}
  
-You will see in the FFT domain a frequency 8 times bigger than the one when the filters where inactive (decimation factor is 8).+You will see in the FFT domain a frequency 8 times bigger than the one when the filters were inactive (decimation factor is 8).
 {{ :resources:fpga:docs:hdl:fmcomms2_fir_rx_active_fft.png?nolink |}} {{ :resources:fpga:docs:hdl:fmcomms2_fir_rx_active_fft.png?nolink |}}
  
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   * {{:resources:fpga:docs:hdl:boot.zip|}}   * {{:resources:fpga:docs:hdl:boot.zip|}}
-  * https://github.com/analogdevicesinc/hdl/tree/fmcomms2_fir_filters+  * https://github.com/analogdevicesinc/hdl/releases/tag/eg_fmcomms2_fir_filter
  
 ===== References  ===== ===== References  =====
  
   * https://uk.mathworks.com/help/dsp/ref/fdesign.interpolator.html   * https://uk.mathworks.com/help/dsp/ref/fdesign.interpolator.html
-  * [[https://wiki.analog.com/resources/fpga/docs/axi_ad9361|axi_ad9361]] +  * [[/resources/fpga/docs/axi_ad9361|axi_ad9361]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] +  * [[/resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] 
-  * [[https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz|AD-FMCOMMS2-EBZ User Guide]] +  * [[/resources/eval/user-guides/ad-fmcomms2-ebz|AD-FMCOMMS2-EBZ User Guide]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/util_upack |util_upack_core]] +  * [[/resources/fpga/docs/util_upack |util_upack_core]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/util_pack |util_pack_core]]+  * [[/resources/fpga/docs/util_cpack |util_pack_core]]
  
  
resources/fpga/docs/hdl/fmcomms2_fir_filt.1495207343.txt.gz · Last modified: 19 May 2017 17:22 by Andrei Grozav

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