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resources:fpga:docs:hdl:fmcomms2_fir_filt [10 Feb 2020 14:55] – Fix broken links Stanca-Florina Popresources:fpga:docs:hdl:fmcomms2_fir_filt [14 Jan 2021 05:24] (current) – use / interwiki links Robin Getz
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 The same approach is implemented on the receive path. The same approach is implemented on the receive path.
 For more information about the reference design visit: For more information about the reference design visit:
-  * [[https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz |fmcomms2 user guide]] +  * [[/resources/eval/user-guides/ad-fmcomms2-ebz |fmcomms2 user guide]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/hdl| HDL user guide]]+  * [[/resources/fpga/docs/hdl| HDL user guide]]
  
 The modified reference design block diagram containing now Interpolation and Decimation filters is presented below. The modified reference design block diagram containing now Interpolation and Decimation filters is presented below.
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 {{ :resources:fpga:docs:hdl:ad9361_dma_data.png?nolink |}} {{ :resources:fpga:docs:hdl:ad9361_dma_data.png?nolink |}}
  
-More information about the util_upack_core [[https://wiki.analog.com/resources/fpga/docs/util_upack |util_upack_core]]+More information about the util_upack_core [[/resources/fpga/docs/util_upack |util_upack_core]]
  
 As a fact the data transmuted/received trough LVDS interface at DDR (Double Data Rate) is presented in the diagram below. As a fact the data transmuted/received trough LVDS interface at DDR (Double Data Rate) is presented in the diagram below.
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 More info on: More info on:
-  * [[https://wiki.analog.com/resources/fpga/docs/build | Building the ADI HDL]] +  * [[/resources/fpga/docs/build | Building the ADI HDL]] 
-  * [[https://wiki.analog.com/resources/tools-software/linux-drivers-all | Building the ADI Linux]]+  * [[/resources/tools-software/linux-drivers-all | Building the ADI Linux]]
  
  
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   * https://uk.mathworks.com/help/dsp/ref/fdesign.interpolator.html   * https://uk.mathworks.com/help/dsp/ref/fdesign.interpolator.html
-  * [[https://wiki.analog.com/resources/fpga/docs/axi_ad9361|axi_ad9361]] +  * [[/resources/fpga/docs/axi_ad9361|axi_ad9361]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] +  * [[/resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] 
-  * [[https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz|AD-FMCOMMS2-EBZ User Guide]] +  * [[/resources/eval/user-guides/ad-fmcomms2-ebz|AD-FMCOMMS2-EBZ User Guide]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/util_upack |util_upack_core]] +  * [[/resources/fpga/docs/util_upack |util_upack_core]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/util_cpack |util_pack_core]]+  * [[/resources/fpga/docs/util_cpack |util_pack_core]]
  
  
resources/fpga/docs/hdl/fmcomms2_fir_filt.txt · Last modified: 14 Jan 2021 05:24 by Robin Getz

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