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resources:fpga:docs:dds [15 Oct 2021 17:15] – Edit footer Iulia Moldovanresources:fpga:docs:dds [23 May 2023 09:37] (current) – fix headlines Andrei Grozav
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 {{ :resources:fpga:docs:dds_in_dac_core.svg |}} {{ :resources:fpga:docs:dds_in_dac_core.svg |}}
  
-The resulting sine-wave can be changed at run time by parameters: +The resulting sine-wave can be changed at run time by parameters:
-  - clock frequency (sampling rate)+
   - frequency word (FW)   - frequency word (FW)
   - phase shift   - phase shift
   - scale (the peak to peak amplitude of the sine-wave)   - scale (the peak to peak amplitude of the sine-wave)
 +  - clock frequency (sampling rate - where possible) 
  
-==== DDS basics ====+===== DDS basics =====
  
 A generic DDS consists of a phase accumulator and a phase to amplitude converter. A generic DDS consists of a phase accumulator and a phase to amplitude converter.
  
-The phase accumulator is basically a counter that increments by a frequency word which determines a timely overflow(the actual period of the signal).+The phase accumulator is basically a counter that increments by a frequency word which determines a timely overflow(the actual period of the resulting signal).
  
 {{ :resources:fpga:docs:dds_basic.svg |}} {{ :resources:fpga:docs:dds_basic.svg |}}
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 The phase to amplitude convertor is a bit more complex and is the main consumer of FPGA resources out of the DDS modules. The phase to amplitude convertor is a bit more complex and is the main consumer of FPGA resources out of the DDS modules.
  
-Currently in the reference designs there are support two types of phase to amplitude converters, polynomial and [[https://en.wikibooks.org/wiki/Digital_Circuits/CORDIC | CORDIC]]. The polynomial type uses more DSPs and less LUTs and FFs than the CORDIC, but at the cost of precision compared to the CORDIC.+Currently in the reference designs there are support two types of phase to amplitude converters, polynomial and [[https://en.wikibooks.org/wiki/Digital_Circuits/CORDIC | CORDIC]]. The polynomial type uses more DSPs and way less LUTs and FFs in comparison to the CORDIC. Regarding precision/accuracy CORDIC is better.
  
-==== ADI DDS module ====+<note>NOTE: The CORDIC implementation is not optimal. The CORDIC phase to amplitude converter outputs a sine and a cosine, which can be used as I and Q. But because the DAC channel reference design requires dual tone + independent I/Q control. only the sine component is used out of a DDS instance, and multiple DDS instances are added for each tone and independent I/Q channels. </note>
  
-=== Parameters ===+===== ADI DDS module ===== 
 + 
 +==== Parameters ====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
 | ''DISABLE'' | Disable DDS | 0 | | ''DISABLE'' | Disable DDS | 0 |
 | ''DDS_DW'' | DDS out data bus width range 8-24 | 16 | | ''DDS_DW'' | DDS out data bus width range 8-24 | 16 |
-| ''PHASE_DW'' | DDS phase accumulator data width. | 16 |+| ''PHASE_DW'' | DDS phase accumulator data width range 8-32. | 16 |
 | ''DDS_TYPE'' | 1 for CORDIC or 2 for Polynomial.  | 1 | | ''DDS_TYPE'' | 1 for CORDIC or 2 for Polynomial.  | 1 |
 | ''CORDIC_DW'' | CORDIC stages data width, range 8-24 | 16 | | ''CORDIC_DW'' | CORDIC stages data width, range 8-24 | 16 |
-| ''CORDIC_PHASE_DW'' | Number of CORDIC stages, range 8-24 (make sure CORDIC_PHASE_DW < CORDIC_DW) | 16 | +| ''CORDIC_PHASE_DW'' | Number of CORDIC stages, range 8-32 | 16 | 
-| ''CLK_RATIO'' | The clock radtio between the device clock(sample rate) and the dac_core clock.  | 0 |+| ''CLK_RATIO'' | The clock ratio between the device clock(axi core clock ~= sample rate) and the interface clock.  | 0 |
  
-=== Interface ===+==== Interface ====
  
 ^ Interface ^ Type ^ Description ^ ^ Interface ^ Type ^ Description ^
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 | ''tone_1_scale''       | ''input[15:0]''                  | Tone 1 scale | | ''tone_1_scale''       | ''input[15:0]''                  | Tone 1 scale |
 | ''tone_2_scale''       | ''input[15:0]''                  | Tone 2 scale | | ''tone_2_scale''       | ''input[15:0]''                  | Tone 2 scale |
-| ''tone_1_init_offset'' | ''input[15:0]''                  | Tone 1 initial offset(phase shift) | +| ''tone_1_init_offset'' | ''input[31:0]''                  | Tone 1 initial offset(phase shift) | 
-| ''tone_2_init_offset'' | ''input[15:0]''                  | Tone 2 initial offset(phase shift) | +| ''tone_2_init_offset'' | ''input[31:0]''                  | Tone 2 initial offset(phase shift) | 
-| ''tone_1_freq_word''   | ''input[15:0]''                  | Tone 1 frequency word | +| ''tone_1_freq_word''   | ''input[31:0]''                  | Tone 1 frequency word | 
-| ''tone_2_freq_word''   | ''input[15:0]''                  | Tone 2 frequency word |+| ''tone_2_freq_word''   | ''input[31:0]''                  | Tone 2 frequency word |
 | ''dac_dds_data''       | ''output[DDS_DW*CLK_RATIO-1:0]'' | Out sine-wave | | ''dac_dds_data''       | ''output[DDS_DW*CLK_RATIO-1:0]'' | Out sine-wave |
 +
 +==== Control ====
  
 In the reference designs the DDS is controlled through the register map(dac channel section). In the reference designs the DDS is controlled through the register map(dac channel section).
-In the register map you cand find the formulas for: 
-  - scale = DDS_SCALE* 
-  - phase shift = DDS_INIT* 
-  - frequency word = DDS_INCR* 
  
-==== ==== 
 {{page>:resources:fpga:docs:hdl:regmap#DAC Channel (axi_ad*)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap#DAC Channel (axi_ad*)&nofooter&noeditbtn}}
  
-=== STRUCTURE ===+===== Config ===== 
 + 
 +\\ 
 + 
 +==== DDS_SCALE ==== 
 + 
 +\\ 
 +The DDS scale for a tone, contributes to the amplitude of the channel(I or Q - where it applies). 
 + 
 +The format is 1.1.14 fixed point. See below: 
 + 
 +^ 16 bit register = scale value ||^ 
 +^ 1 bit sign ^ 1 bit integer^ 14 bits fractional^ 
 + 
 +The DDS scale is on 16-bits. 
 + 
 +The channel output is equal to (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). 
 + 
 +The phase to amplitude converter always outputs the full-scale(unity sine) sinewave, independent on the phase and data widths. 
 + 
 +<note>NOTE: if you do use both tones and set both scales to 0x4000, the channel output will over-range.</note> 
 + 
 +16'h4000 * 1 + 16'h4000 * 1 = 16'h8000 = 16'h1000000000000000 
 + 
 +  - sign = 1'b1 
 +  - integer = 1'b0 
 +  - fract = 14'b0 
 + 
 +\\ 
 + 
 +==== PHASE - DDS_INIT ==== 
 + 
 +\\ 
 + 
 +All tones/channels start on a sync event(internal or external). The DDS_INIT value will be used by the phase accumulator as a starting point in other words as a phase offset. 
 + 
 +The offset can be determined from the phase accumulator capacity 0 to <m>2^phaseDW</m> represents (0° - 360°). 
 + 
 +e.g. for 90°. init = (90 * <m>2^phaseDW</m>)/360 
 + 
 +\\ 
 + 
 +==== FREQUENCY - DDS_INCR ==== 
 + 
 +\\ 
 + 
 +The value can be calculated by <m>INCR = (f_out * 2^phaseDW) * clkratio / f_if</m>; 
 + 
 +Where: 
 +  - f_out is the generated output frequency 
 +  - phaseDW(DDS_PHASE_DW) value can be found in REG_CHAN_CNTRL_1 in case DDS_PHASE_DW is not eq. 16 
 +  - f_if is the frequency of the digital interface 
 +  - clock_ratio is the ratio between the sampling clock and the interface clock. 
 + 
 +\\ 
 + 
 +===== STRUCTURE =====
  
 Below is the hierarchical structure of the modules. Below is the hierarchical structure of the modules.
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         * ad_dds_sine_*         * ad_dds_sine_*
  
-=== ad_dds ===+==== ad_dds ====
  
 [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds.v|ad_dds]] is the main module, it contains the phase accumulators and the phase to amplitude converters. [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds.v|ad_dds]] is the main module, it contains the phase accumulators and the phase to amplitude converters.
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 {{ :resources:fpga:docs:dds_dual_tone.svg |}} {{ :resources:fpga:docs:dds_dual_tone.svg |}}
  
-=== ad_dds_2 ===+==== ad_dds_2 ====
  
 [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds_2.v|ad_dds_2]] contains two phase to amplitude converters. The resulting wave-forms will be summed. The resulting wave-form must have a maximum amplitude level of 0x8000 -1. When only one tone is desired both tones must have the same frequency word and shift, there is no constraint for the amplitude, but if is equal for both channels, it should not be more than 0x400 -1 for each channel. [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds_2.v|ad_dds_2]] contains two phase to amplitude converters. The resulting wave-forms will be summed. The resulting wave-form must have a maximum amplitude level of 0x8000 -1. When only one tone is desired both tones must have the same frequency word and shift, there is no constraint for the amplitude, but if is equal for both channels, it should not be more than 0x400 -1 for each channel.
  
-=== ad_dds_1 ===+==== ad_dds_1 ====
 [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds_1.v|ad_dds_1]] contains the phase to amplitude converter and an "amplifier". The phase to amplitude converter is always generating a full scale sine-wave. Because the data format is two's complement, for a 16 bit data angle, min value will be -(2^16)/2 and max (2^16)/2-1. [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds_1.v|ad_dds_1]] contains the phase to amplitude converter and an "amplifier". The phase to amplitude converter is always generating a full scale sine-wave. Because the data format is two's complement, for a 16 bit data angle, min value will be -(2^16)/2 and max (2^16)/2-1.
  
 {{ :resources:fpga:docs:ad_dds_1.svg |}} {{ :resources:fpga:docs:ad_dds_1.svg |}}
  
-=== ad_dds_sine_* ===+==== ad_dds_sine_* ====
  
 [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds_sine.v|ad_dds_sine]] and [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds_sine_cordic.v|ad_dds_sine_cordic]] are the available phase to amplitude converters. [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds_sine.v|ad_dds_sine]] and [[http://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds_sine_cordic.v|ad_dds_sine_cordic]] are the available phase to amplitude converters.
  
-=== CLOCK RATIO ===+==== CLOCK RATIO ====
  
 The clock ratio (number data paths processed in parallel) instantiates more DDS logic, but it it is controlled by the same register map for all CLOCK_RATIO/DATA_PATH parameters. The clock ratio (number data paths processed in parallel) instantiates more DDS logic, but it it is controlled by the same register map for all CLOCK_RATIO/DATA_PATH parameters.
resources/fpga/docs/dds.txt · Last modified: 23 May 2023 09:37 by Andrei Grozav