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| resources:fpga:docs:data_offload [11 Aug 2022 11:42] – [Features] Laszlo Nagy | resources:fpga:docs:data_offload [11 Aug 2022 12:08] (current) – Register map updates Laszlo Nagy |
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| | ''ID'' | Instance identification number. | 0 | | | ''ID'' | Instance identification number. | 0 | |
| | ''MEM_TYPE'' | Define the used storage type: 0: BlockRAM; 1: external DDR | 0 | | | ''MEM_TYPE'' | Define the used storage type: 0: BlockRAM; 1: external DDR | 0 | |
| | ''MEM_SIZE'' | Define the size of the storage element in bytes | 1024 | | | ''MEM_SIZE_LOG2'' | Define the log2 size of the storage element in bytes | 10 | |
| | ''MEMC_UIF_DATA_WIDTH'' | The valid data depends on the DDRx memory controller IP. | 512 | | |
| | ''TX_OR_RXN_PATH'' | If set TX path enabled, otherwise RX | 1 | | | ''TX_OR_RXN_PATH'' | If set TX path enabled, otherwise RX | 1 | |
| | ''SRC_DATA_WIDTH'' | The data width of the source interface | 64 | | | ''SRC_DATA_WIDTH'' | The data width of the source interface | 64 | |
| | ''SRC_RAW_DATA_EN'' | Enable if the data path does extend samples to 16 bits | 0 | | |
| | ''SRC_ADDR_WIDTH'' | The address width of the source interface, should be defined relative to the MEM_SIZE (MEM_SIZE/SRC_DATA_WIDTH/8) | 8 | | |
| | ''DST_ADDR_WIDTH'' | The address width of the source interface, should be defined relative to the MEM_SIZE (MEM_SIZE/DST_DATA_WIDTH/8) | 7 | | |
| | ''DST_DATA_WIDTH'' | The data width of the destination interface | 64 | | | ''DST_DATA_WIDTH'' | The data width of the destination interface | 64 | |
| | ''DST_RAW_DATA_EN'' | Enable if the data path does extend samples to 16 bits | 0 | | |
| | ''DST_CYCLIC_EN'' | Enables CYCLIC mode for destinations like DAC | 0 | | | ''DST_CYCLIC_EN'' | Enables CYCLIC mode for destinations like DAC | 0 | |
| | ''AUTO_BRINUP'' | If enabled the IP runs automatically after bootup | 0 | | | ''AUTO_BRINUP'' | If enabled the IP runs automatically after bootup | 0 | |
| | | ''SYNC_EXT_ADD_INTERNAL_CDC '' | If enabled the CDC circuitry for the external sync signal is added | 0 | |
| | | ''HAS_BYPASS '' | If enabled the bypass circuitry is added | 0 | |
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| ===== Signal and Interface Pins ===== | ===== Signal and Interface Pins ===== |
| | | | [31:0] | IDENTIFICATION | RW | 0x44414F46 | MAGIC peripheral identifier, can be used to verify that you're actually talking to a data offload | | | | | [31:0] | IDENTIFICATION | RW | 0x44414F46 | MAGIC peripheral identifier, can be used to verify that you're actually talking to a data offload | |
| ^ 0x0004 ^ 0x0010 ^ SYNTHESIS_CONFIG ||||| | ^ 0x0004 ^ 0x0010 ^ SYNTHESIS_CONFIG ||||| |
| | | | | [13: 8] | MEM_SIZE_LOG2| RO | | Log2 of memory size in bytes| |
| | | | | [2:2] | HAS_BYPASS | RO | | If not set the bypass logic is not implemented. | |
| | | | [1:1] | TX_OR_RXN_PATH | RO | | If this device was configured for the TX path, this bit will be set to 1. Conversely, the bit will be 0 for the RX path. | | | | | [1:1] | TX_OR_RXN_PATH | RO | | If this device was configured for the TX path, this bit will be set to 1. Conversely, the bit will be 0 for the RX path. | |
| | ::: | ::: | [0:0] | MEMORY_TYPE | RO | | This bit identifies the type of memory that was chosen during synthesis. A value of 1 identifies external memory, while a value of zero indicates that block ram was used | | | ::: | ::: | [0:0] | MEMORY_TYPE | RO | | This bit identifies the type of memory that was chosen during synthesis. A value of 1 identifies external memory, while a value of zero indicates that block ram was used | |
| ^ 0x0005 ^ 0x0014 ^ MEMORY_SIZE_LSB ||||| | |
| | | | [31:0] | MEMORY_SIZE_LSB | RO | | The 32-LSBs of the total memory size in bytes. Together with the two MSBs from next next register, this value indicates how much memory was used to synthesis this data offload ^ | |
| ^ 0x0006 ^ 0x0018 ^ MEMORY_SIZE_MSB ||||| | |
| | | | [1:0] | MEMORY_SIZE_MSB | RO | | The two MSBs of the total memory size in bytes | | |
| ^ 0x0007 ^ 0x001c ^ TRANSFER_LENGTH ||||| | ^ 0x0007 ^ 0x001c ^ TRANSFER_LENGTH ||||| |
| | | | [31:0] | TRANSFER_LENGTH | RW | | The transfer length register can be used to override the transfer length in RX mode in increments of 64 bytes | | | | | [31:0] | TRANSFER_LENGTH | RW | | The transfer length register can be used to override the transfer length in RX mode in increments of 64 bytes | |
| ^ 0x0020 ^ 0x0080 ^ MEM_PHY_STATE ||||| | ^ 0x0020 ^ 0x0080 ^ MEM_PHY_STATE ||||| |
| | | | | [5:5] | UNDERFLOW | RO | | Indicates that storage could not handle data rate during play. Available when core is in TX mode. | |
| | | | | [4:4] | OVERFLOW | RO | | Indicates that storage could not handle data rate during capture. Available when core is in RX mode. | |
| | | | [0:0] | CALIB_COMPLETE | RO | | Information about the memory phy for setups with external (DDR) storage. Indicates that the memory initialization and calibration have completed | | | | | [0:0] | CALIB_COMPLETE | RO | | Information about the memory phy for setups with external (DDR) storage. Indicates that the memory initialization and calibration have completed | |
| ^ 0x0021 ^ 0x0084 ^ RESETN_OFFLOAD ||||| | ^ 0x0021 ^ 0x0084 ^ RESETN_OFFLOAD ||||| |
| | | | [1:0] | SYNC_CONFIG | RW | | Synchronization mode: 0: auto, 1: external hardware trigger, 2: software trigger (See SYNC_TRIGGER), 3: RESERVED/FORBIDDEN VALUE. | | | | [1:0] | SYNC_CONFIG | RW | | Synchronization mode: 0: auto, 1: external hardware trigger, 2: software trigger (See SYNC_TRIGGER), 3: RESERVED/FORBIDDEN VALUE. |
| ^ 0x0080 ^ 0x0200 ^ FSM_DBG ||||| | ^ 0x0080 ^ 0x0200 ^ FSM_DBG ||||| |
| | | | [5:4] | FSM_STATE_READ | RO | | The current read / output FSM state. | | | | | [11:8] | FSM_STATE_READ | RO | | The current read / output FSM state. | |
| | ::: | ::: | [1:0] | FSM_STATE_WRITE | RO | | The current write / input FSM state. | | | ::: | ::: | [4:0] | FSM_STATE_WRITE | RO | | The current write / input FSM state. | |
| ^ 0x0081 ^ 0x0204 ^ SAMPLE_COUNT_LSB ||||| | ^ 0x0081 ^ 0x0204 ^ SAMPLE_COUNT_LSB ||||| |
| | | | [31:0] | SAMPLE_COUNT_LSB | RO | | Current input beat count, 32 LSBs, for debug purposes | | |
| ^ 0x0082 ^ 0x0208 ^ SAMPLE_COUNT_MSB ||||| | |
| | | | [31:0] | SAMPLE_COUNT_MSB | RO | | Current input beat count, 32 MSBs, for debug purposes | | |
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| </hidden> | </hidden> |
