| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| resources:fpga:docs:axi_tdd [07 Oct 2022 06:40] – [Detailed description] Ionut Podgoreanu | resources:fpga:docs:axi_tdd [27 Jul 2023 21:56] (current) – Removed obsolete linux references Ionut Podgoreanu |
|---|
| * Configurable frame length and number of frames per burst | * Configurable frame length and number of frames per burst |
| * 3 sources of synchronization: external, internal and software generated | * 3 sources of synchronization: external, internal and software generated |
| |
| |
| ===== Utilization ===== | |
| |
| ^ Device Family ^ LUTs ^ FFs ^ | |
| | Xilinx Zynq UltraScale+ | 990 | 2738 | | |
| |
| |
| |
| ^ Name ^ Description ^ | ^ Name ^ Description ^ |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd.sv|axi_tdd.sv]] | Top module | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd.sv|axi_tdd.sv]] | Top module | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_pkg.sv|axi_tdd_pkg.sv]] | SystemVerilog Package | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_pkg.sv|axi_tdd_pkg.sv]] | SystemVerilog Package | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_regmap.sv|axi_tdd_regmap.sv]] | Register Map with CDC synchronizers | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_regmap.sv|axi_tdd_regmap.sv]] | Register Map with CDC synchronizers | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_counter.sv|axi_tdd_counter.sv]] | Internal counters and FSM logic | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_counter.sv|axi_tdd_counter.sv]] | Internal counters and FSM logic | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_channel.sv|axi_tdd_channel.sv]] | Channel waveform generator | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_channel.sv|axi_tdd_channel.sv]] | Channel waveform generator | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_sync_gen.sv|axi_tdd_sync_gen.sv]] | Synchronization pulse generator | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_sync_gen.sv|axi_tdd_sync_gen.sv]] | Synchronization pulse generator | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_ip.tcl|axi_tdd_ip.tcl]] | TCL script to generate the Vivado IP-integrator project | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_ip.tcl|axi_tdd_ip.tcl]] | TCL script to generate the Vivado IP-integrator project | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_hw.tcl|axi_tdd_hw.tcl]] | TCL script to generate the Quartus IP-integrator project | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_hw.tcl|axi_tdd_hw.tcl]] | TCL script to generate the Quartus IP-integrator project | |
| | [[https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/cf_axi_tdd.c|cf_axi_tdd.c]] | TDD Linux Driver | | |
| | [[https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts|zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts]] | Device tree using TDD | | |
| |
| |
| | ''SYNC_COUNT_WIDTH'' | Sync generator counter width | 64 | 64 | | | ''SYNC_COUNT_WIDTH'' | Sync generator counter width | 64 | 64 | |
| ===== Signal and Interface Pins ===== | ===== Signal and Interface Pins ===== |
| | |
| | {{:resources:fpga:docs:axi_tdd:axi_tdd_vivado.png|}} |
| |
| ^ Name ^ Type ^ Description ^ | ^ Name ^ Type ^ Description ^ |
| |< 100% 10em 10em >| | |< 100% 10em 10em >| |
| ^ Access Type ^ Name ^ Description ^ | ^ Access Type ^ Name ^ Description ^ |
| | HR | Hardware-reset | Register field is reset by hardware. | | |
| | R | Read-only | Reads will return the current register value. Writes have no effect. | | | R | Read-only | Reads will return the current register value. Writes have no effect. | |
| | RW | Read-write | Reads will return the current register value. Writes will change the current register value. | | | RW | Read-write | Reads will return the current register value. Writes will change the current register value. | |
| {{:resources:fpga:docs:axi_tdd:axi_tdd_diagram.png|}} | {{:resources:fpga:docs:axi_tdd:axi_tdd_diagram.png|}} |
| |
| This diagram tries to illustrate how the different channels can be enabled at different times relative to the beginning of a frame (to be updated) | This diagram tries to illustrate how the different channels can be enabled at different times relative to the beginning of a frame. |
| |
| <note tip>While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other!</note> | <note tip>While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other!</note> |
| |
| By adapting the synthesis parameters to the application requirements, the module is highly flexible and can substantially reduce resource utilization. | By adapting the synthesis parameters to the application requirements, the module is highly flexible and can substantially reduce resource utilization. |
| |
| ===== Linux IIO Driver ===== | |
| |
| The [[https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/cf_axi_tdd.c|linux driver]] defines an iio interface. The driver can be instantiated in the device tree as follows: | |
| |
| <code> | |
| axi_tdd_0: axi-tdd-0@9c460000 { | |
| compatible = "adi,axi-tdd-1.00"; | |
| reg = <0x9c460000 0x10000>; | |
| clocks = <&zynqmp_clk PL0_REF>, <&hmc7044 6>; | |
| clock-names = "s_axi_aclk", "intf_clk"; | |
| }; | |
| </code> | |
| |
| <note tip> | |
| The driver needs to know which clock is driving the main clock input ''clk'' to calculate the required register values from the times provided to the iio attributes (''T / clk_rate''). | |
| </note> | |
| |
| The resulting IIO device looks like this, where there is one channel per combination of ''rx'', ''tx'' and ''primary'', ''secondary''. Keep in mind that these channels are only used to structure their attributes, and don't carry any information themselves. | |
| <code> | |
| iio:device2: axi-core-tdd | |
| 4 channels found: | |
| data1: (output, WARN:iio_channel_get_type()=UNKNOWN) | |
| 6 channel-specific attributes found: | |
| attr 0: dp_off_ms value: 0 | |
| attr 1: dp_on_ms value: 0 | |
| attr 2: off_ms value: 0 | |
| attr 3: on_ms value: 0 | |
| attr 4: vco_off_ms value: 0 | |
| attr 5: vco_on_ms value: 0 | |
| data1: (input, WARN:iio_channel_get_type()=UNKNOWN) | |
| 6 channel-specific attributes found: | |
| attr 0: dp_off_ms value: 0 | |
| attr 1: dp_on_ms value: 0 | |
| attr 2: off_ms value: 0 | |
| attr 3: on_ms value: 0 | |
| attr 4: vco_off_ms value: 0 | |
| attr 5: vco_on_ms value: 0 | |
| data0: (output, WARN:iio_channel_get_type()=UNKNOWN) | |
| 6 channel-specific attributes found: | |
| attr 0: dp_off_ms value: 0 | |
| attr 1: dp_on_ms value: 0 | |
| attr 2: off_ms value: 0 | |
| attr 3: on_ms value: 0 | |
| attr 4: vco_off_ms value: 0 | |
| attr 5: vco_on_ms value: 0 | |
| data0: (input, WARN:iio_channel_get_type()=UNKNOWN) | |
| 6 channel-specific attributes found: | |
| attr 0: dp_off_ms value: 0 | |
| attr 1: dp_on_ms value: 0 | |
| attr 2: off_ms value: 0 | |
| attr 3: on_ms value: 0 | |
| attr 4: vco_off_ms value: 0 | |
| attr 5: vco_on_ms value: 0 | |
| 10 device-specific attributes found: | |
| attr 0: burst_count value: 0 | |
| attr 1: counter_int value: 0 | |
| attr 2: dma_gateing_mode value: rx_tx | |
| attr 3: dma_gateing_mode_available value: rx_tx rx_only tx_only none | |
| attr 4: en value: 0 | |
| attr 5: en_mode value: rx_tx | |
| attr 6: en_mode_available value: rx_tx rx_only tx_only | |
| attr 7: frame_length_ms value: 0 | |
| attr 8: secondary value: 0 | |
| attr 9: sync_terminal_type value: 0 | |
| 1 debug attributes found: | |
| debug attr 0: direct_reg_access value: 0x10061 | |
| No trigger on this device | |
| </code> | |
| |
| | [[https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts|zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts]] | Device tree using TDD | | |
| |
| |
| {{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}} | {{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}} |
