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| resources:fpga:docs:axi_tdd [07 Oct 2022 06:15] – [Register Map] Ionut Podgoreanu | resources:fpga:docs:axi_tdd [27 Jul 2023 21:56] (current) – Removed obsolete linux references Ionut Podgoreanu |
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| * Configurable frame length and number of frames per burst | * Configurable frame length and number of frames per burst |
| * 3 sources of synchronization: external, internal and software generated | * 3 sources of synchronization: external, internal and software generated |
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| ===== Utilization ===== | |
| |
| ^ Device Family ^ LUTs ^ FFs ^ | |
| | Xilinx Zynq UltraScale+ | 990 | 2738 | | |
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| ^ Name ^ Description ^ | ^ Name ^ Description ^ |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd.sv|axi_tdd.sv]] | Top module | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd.sv|axi_tdd.sv]] | Top module | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_pkg.sv|axi_tdd_pkg.sv]] | SystemVerilog Package | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_pkg.sv|axi_tdd_pkg.sv]] | SystemVerilog Package | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_regmap.sv|axi_tdd_regmap.sv]] | Register Map with CDC synchronizers | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_regmap.sv|axi_tdd_regmap.sv]] | Register Map with CDC synchronizers | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_counter.sv|axi_tdd_counter.sv]] | Internal counters and FSM logic | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_counter.sv|axi_tdd_counter.sv]] | Internal counters and FSM logic | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_channel.sv|axi_tdd_channel.sv]] | Channel waveform generator | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_channel.sv|axi_tdd_channel.sv]] | Channel waveform generator | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_sync_gen.sv|axi_tdd_sync_gen.sv]] | Synchronization pulse generator | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_sync_gen.sv|axi_tdd_sync_gen.sv]] | Synchronization pulse generator | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_ip.tcl|axi_tdd_ip.tcl]] | TCL script to generate the Vivado IP-integrator project | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_ip.tcl|axi_tdd_ip.tcl]] | TCL script to generate the Vivado IP-integrator project | |
| | [[https://github.com/analogdevicesinc/hdl/blob/dev_tdd_pr/library/axi_tdd/axi_tdd_hw.tcl|axi_tdd_hw.tcl]] | TCL script to generate the Quartus IP-integrator project | | | [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_tdd/axi_tdd_hw.tcl|axi_tdd_hw.tcl]] | TCL script to generate the Quartus IP-integrator project | |
| | [[https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/cf_axi_tdd.c|cf_axi_tdd.c]] | TDD Linux Driver | | |
| | [[https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts|zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts]] | Device tree using TDD | | |
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| | ''SYNC_COUNT_WIDTH'' | Sync generator counter width | 64 | 64 | | | ''SYNC_COUNT_WIDTH'' | Sync generator counter width | 64 | 64 | |
| ===== Signal and Interface Pins ===== | ===== Signal and Interface Pins ===== |
| | |
| | {{:resources:fpga:docs:axi_tdd:axi_tdd_vivado.png|}} |
| |
| ^ Name ^ Type ^ Description ^ | ^ Name ^ Type ^ Description ^ |
| |< 100% 10em 10em >| | |< 100% 10em 10em >| |
| ^ Access Type ^ Name ^ Description ^ | ^ Access Type ^ Name ^ Description ^ |
| | HR | Hardware-reset | Register field is reset by hardware. | | |
| | R | Read-only | Reads will return the current register value. Writes have no effect. | | | R | Read-only | Reads will return the current register value. Writes have no effect. | |
| | RW | Read-write | Reads will return the current register value. Writes will change the current register value. | | | RW | Read-write | Reads will return the current register value. Writes will change the current register value. | |
| ===== Theory of Operation ===== | ===== Theory of Operation ===== |
| |
| The central idea of the TDD controller is “frame”-based operation, i.e. all the timing defined for the individual channels is relative to the beginning of a frame. The ''TDD_FRAME_LENGTH'' value controls the length of a single frame, while the ''TDD_BURST_COUNT'' value controls how many frames should be played after enabling the device (a value of 0 means frames will be repeated indefinitely). Before the start of a burst, an optional startup delay is inserted, defined by the ''TDD_STARTUP_DELAY'' value in clock cycles. | The central idea of the TDD controller is “frame”-based operation, i.e. all the timing defined for the individual channels is relative to the beginning of a frame. The ''FRAME_LENGTH'' value controls the length of a single frame, while the ''BURST_COUNT'' value controls how many frames should be played after enabling the device (a value of 0 means frames will be repeated indefinitely). Before the start of a burst, an optional startup delay is inserted, defined by the ''STARTUP_DELAY'' value in clock cycles. |
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| {{:resources:fpga:docs:axi_tdd:axi_tdd_diagram.png|}} | {{:resources:fpga:docs:axi_tdd:axi_tdd_diagram.png|}} |
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| This diagram tries to illustrate how the different channels can be enabled at different times relative to the beginning of a frame (to be updated) | This diagram tries to illustrate how the different channels can be enabled at different times relative to the beginning of a frame. |
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| <note tip>While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other!</note> | <note tip>While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other!</note> |
| ==== Detailed description ==== | ==== Detailed description ==== |
| |
| In order to begin its operation, the peripheral must be enabled. This is done by setting the ''TDD_ENABLE'' bit. Next, the peripheral waits to receive a sync signal. There are 3 possible sync sources, which can be independently activated through their corresponding enabling bits: ''TDD_SYNC_INT'', ''TDD_SYNC_EXT'' and ''TDD_SYNC_SOFT'' can all be active at the same time. | In order to begin its operation, the peripheral must be enabled. This is done by setting the ''ENABLE'' bit. Next, the peripheral waits to receive a sync signal. There are 3 possible sync sources, which can be independently activated through their corresponding enabling bits: ''SYNC_INT'', ''SYNC_EXT'' and ''SYNC_SOFT'' can all be active at the same time. |
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| The external synchronization capability allows the alignment of frames between multiple devices in different locations, for example using a GPSDO 1 PPS output. The internal sync signal is generated based on a dedicated counter, when its value matches the one defined in ''TDD_SYNC_COUNTER_LOW'' / ''TDD_SYNC_COUNTER_HIGH''. The software generated sync pulse is triggered at an arbitrary point in time when writing a ‘1’ value in ''TDD_SYNC_SOFT''. | The external synchronization capability allows the alignment of frames between multiple devices in different locations, for example using a GPSDO 1 PPS output. The internal sync signal is generated based on a dedicated counter, when its value matches the one defined in ''SYNC_COUNTER_LOW'' / ''SYNC_COUNTER_HIGH''. The software generated sync pulse is triggered at an arbitrary point in time when writing a ‘1’ value in ''SYNC_SOFT''. |
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| The next diagram shows the peripheral’s FSM, which transitions between 4 states: IDLE, ARMED, WAITING and RUNNING. (to be updated) | The next diagram shows the peripheral’s FSM, which transitions between 4 states: IDLE, ARMED, WAITING and RUNNING. |
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| In case a synchronization signal is received while the TDD core is running, the signal can reset the internal counter to zero by setting ''TDD_SYNC_RST'' to ‘1’. This can alter the counter value in both WAITING or RUNNING states. | {{:resources:fpga:docs:axi_tdd:axi_tdd_fsm.png?500|}} |
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| The generic TDD controller can have up to 32 output channels, each of them having its unique values when the channel is set/reset under ''TDD_CHX_ON'' / ''TDD_CHX_OFF''. They are continuously compared to internal counter’s value while the core is RUNNING. | In case a synchronization signal is received while the TDD core is running, the signal can reset the internal counter to zero by setting ''SYNC_RST'' to ‘1’. This can alter the counter value in both WAITING or RUNNING states. |
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| Every bit in ''TDD_CH_ENABLE'' / ''TDD_CH_POLARITY'' corresponds to a specific channel. The bit position is correlated to the channel index, so the LSB will always be associated with CH0 and the MSB with CH31. | The generic TDD controller can have up to 32 output channels, each of them having its unique values when the channel is set/reset under ''CHX_ON'' / ''CHX_OFF''. They are continuously compared to internal counter’s value while the core is RUNNING. |
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| | Every bit in ''CHANNEL_ENABLE'' / ''CHANNEL_POLARITY'' corresponds to a specific channel. The bit position is correlated to the channel index, so the LSB will always be associated with CH0 and the MSB with CH31. |
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| The following registers will not be updated unless the peripheral is disabled: | The following registers will not be updated unless the peripheral is disabled: |
| * REG_TDD_BURST_COUNT | * ''BURST_COUNT'' |
| * REG_TDD_STARTUP_DELAY | * ''STARTUP_DELAY'' |
| * REG_TDD_FRAME_LENGTH | * ''FRAME_LENGTH'' |
| * REG_TDD_CHANNEL_POLARITY | * ''CHANNEL_POLARITY'' |
| * REG_TDD_SYNC_COUNTER_LOW | * ''SYNC_COUNTER_LOW'' |
| * REG_TDD_SYNC_COUNTER_HIGH | * ''SYNC_COUNTER_HIGH'' |
| * REG_TDD_CHX_ON | * ''CHX_ON'' |
| * REG_TDD_CHX_OFF | * ''CHX_OFF'' |
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| The user should configure them before enabling the peripheral. Any subsequent write while the peripheral is enabled will be ignored. | The user should configure them before enabling the peripheral. Any subsequent write while the peripheral is enabled will be ignored. |
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| An exception to this rule is REG_TDD_CHANNEL_ENABLE, which allows enabling / disabling independent channels on-the-fly. The new value will come into effect only when in ARMED state or at the end of a frame. REG_TDD_CONTROL can also be modified on-the-fly with immediate effect (after going through the synchronization stage). | An exception to this rule is ''CHANNEL_ENABLE'', which allows enabling / disabling independent channels on-the-fly. The new value will come into effect only when in ARMED state or at the end of a frame. ''CONTROL'' can also be modified on-the-fly with immediate effect (after going through the synchronization stage). |
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| REG_TDD_STATUS can be used for debugging purposes, reflecting the current peripheral state. | ''STATUS'' can be used for debugging purposes, reflecting the current peripheral state. |
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| By adapting the synthesis parameters to the application requirements, the module is highly flexible and can substantially reduce resource utilization. | By adapting the synthesis parameters to the application requirements, the module is highly flexible and can substantially reduce resource utilization. |
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| ===== Linux IIO Driver ===== | |
| |
| The [[https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/cf_axi_tdd.c|linux driver]] defines an iio interface. The driver can be instantiated in the device tree as follows: | |
| |
| <code> | |
| axi_tdd_0: axi-tdd-0@9c460000 { | |
| compatible = "adi,axi-tdd-1.00"; | |
| reg = <0x9c460000 0x10000>; | |
| clocks = <&zynqmp_clk PL0_REF>, <&hmc7044 6>; | |
| clock-names = "s_axi_aclk", "intf_clk"; | |
| }; | |
| </code> | |
| |
| <note tip> | |
| The driver needs to know which clock is driving the main clock input ''clk'' to calculate the required register values from the times provided to the iio attributes (''T / clk_rate''). | |
| </note> | |
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| The resulting IIO device looks like this, where there is one channel per combination of ''rx'', ''tx'' and ''primary'', ''secondary''. Keep in mind that these channels are only used to structure their attributes, and don't carry any information themselves. | |
| <code> | |
| iio:device2: axi-core-tdd | |
| 4 channels found: | |
| data1: (output, WARN:iio_channel_get_type()=UNKNOWN) | |
| 6 channel-specific attributes found: | |
| attr 0: dp_off_ms value: 0 | |
| attr 1: dp_on_ms value: 0 | |
| attr 2: off_ms value: 0 | |
| attr 3: on_ms value: 0 | |
| attr 4: vco_off_ms value: 0 | |
| attr 5: vco_on_ms value: 0 | |
| data1: (input, WARN:iio_channel_get_type()=UNKNOWN) | |
| 6 channel-specific attributes found: | |
| attr 0: dp_off_ms value: 0 | |
| attr 1: dp_on_ms value: 0 | |
| attr 2: off_ms value: 0 | |
| attr 3: on_ms value: 0 | |
| attr 4: vco_off_ms value: 0 | |
| attr 5: vco_on_ms value: 0 | |
| data0: (output, WARN:iio_channel_get_type()=UNKNOWN) | |
| 6 channel-specific attributes found: | |
| attr 0: dp_off_ms value: 0 | |
| attr 1: dp_on_ms value: 0 | |
| attr 2: off_ms value: 0 | |
| attr 3: on_ms value: 0 | |
| attr 4: vco_off_ms value: 0 | |
| attr 5: vco_on_ms value: 0 | |
| data0: (input, WARN:iio_channel_get_type()=UNKNOWN) | |
| 6 channel-specific attributes found: | |
| attr 0: dp_off_ms value: 0 | |
| attr 1: dp_on_ms value: 0 | |
| attr 2: off_ms value: 0 | |
| attr 3: on_ms value: 0 | |
| attr 4: vco_off_ms value: 0 | |
| attr 5: vco_on_ms value: 0 | |
| 10 device-specific attributes found: | |
| attr 0: burst_count value: 0 | |
| attr 1: counter_int value: 0 | |
| attr 2: dma_gateing_mode value: rx_tx | |
| attr 3: dma_gateing_mode_available value: rx_tx rx_only tx_only none | |
| attr 4: en value: 0 | |
| attr 5: en_mode value: rx_tx | |
| attr 6: en_mode_available value: rx_tx rx_only tx_only | |
| attr 7: frame_length_ms value: 0 | |
| attr 8: secondary value: 0 | |
| attr 9: sync_terminal_type value: 0 | |
| 1 debug attributes found: | |
| debug attr 0: direct_reg_access value: 0x10061 | |
| No trigger on this device | |
| </code> | |
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| | [[https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts|zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts]] | Device tree using TDD | | |
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| {{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}} | {{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}} |
