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resources:fpga:docs:axi_ltc2387 [27 Sep 2022 15:16] Iulia Moldovan Add link to HDL architecture |
resources:fpga:docs:axi_ltc2387 [22 Feb 2023 18:18] Iulia Moldovan Added note about one lane restrictions |
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| == ADC_DATA == | == ADC_DATA == | ||
| - | Depending on ''TWOLANES'' parameter, whether it is set or not, the output adc_data is either taken from the DA+/- port interleaved with bits from DB+/-, or it is taken only from DA+/- port. \\ | + | Depending on ''TWOLANES'' parameter, whether it is set or not, the output //adc_data// is either taken from the DA+/- port interleaved with bits from DB+/-, or it is taken only from DA+/- port. \\ |
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| + | <note>Note that when using the **ONE LANE** configuration, the only resolution available is **18 bits**!</note> | ||
| ==== Channel module description ==== | ==== Channel module description ==== | ||
resources/fpga/docs/axi_ltc2387.txt · Last modified: 22 Feb 2023 18:18 by Iulia Moldovan