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resources:fpga:docs:axi_logic_analyzer [31 May 2017 10:16] – Adrian Costina | resources:fpga:docs:axi_logic_analyzer [13 Oct 2021 10:03] (current) – Edit footer & add reference to generic ADC Iulia Moldovan | ||
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- | ===== AXI_LOGIC_ANALYZER ===== | + | ====== AXI_LOGIC_ANALYZER |
- | The AXI_LOGIC_ANALYZER IP implements both an logic analyzer and a pattern generator, sharing the same pins | + | The AXI_LOGIC_ANALYZER IP implements both a logic analyzer and a pattern generator, sharing the same pins\\ |
+ | \\ | ||
+ | More about the generic framework interfacing ADCs can be read here: [[: | ||
- | ==== Features ==== | + | |
+ | ===== Features | ||
* AXI Lite control/ | * AXI Lite control/ | ||
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* Control history variable FIFO | * Control history variable FIFO | ||
- | ==== Block Diagram ==== | ||
- | {{ : | + | ===== Block Diagram ===== |
- | ==== Interface ==== | + | AXI logic analyzer main module: |
+ | |||
+ | {{: | ||
+ | |||
+ | Logic analyzer trigger submodule: | ||
+ | {{: | ||
+ | |||
+ | |||
+ | ===== Interface | ||
^ Interface ^ Pin ^ Type ^ Description ^ | ^ Interface ^ Pin ^ Type ^ Description ^ | ||
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| | '' | | | '' | ||
| | '' | | | '' | ||
+ | | | '' | ||
+ | | | '' | ||
+ | | | '' | ||
| **Pattern generator path** | | **Pattern generator path** | ||
| | '' | | | '' | ||
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| **Trigger** | ||| | | **Trigger** | ||| | ||
| |'' | | |'' | ||
- | | |'' | + | | |'' |
| **AXI_S_MM interface** |||| | | **AXI_S_MM interface** |||| | ||
| | '' | | | '' | ||
- | ==== Detailed Description ==== | + | |
+ | ===== Detailed Description | ||
The AXI_LOGIC_ANALYZER IP implements both a logic analyzer and a pattern generator functionality. | The AXI_LOGIC_ANALYZER IP implements both a logic analyzer and a pattern generator functionality. | ||
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The same thing is done for the pattern generator using the up sampling block. | The same thing is done for the pattern generator using the up sampling block. | ||
- | Triggering for the logic analyzer is implemented in this IP also. It can generate triggers based on ext trigger signals and the 16 bit input signals. | + | The logic analyzer, can be synchronized(data delayed) to the ADC path() |
+ | |||
+ | Triggering for the logic analyzer is implemented in this IP also. It can generate triggers based on ext trigger signals, ADC(Oscilloscope) trigger | ||
In order to provide data before triggering, a variable length FIFO should be used with this IP. The length of the FIFO is configured through the TRIGGER_DELAY register. It can be bypassed if TRIGGER_DELAY is 0. | In order to provide data before triggering, a variable length FIFO should be used with this IP. The length of the FIFO is configured through the TRIGGER_DELAY register. It can be bypassed if TRIGGER_DELAY is 0. | ||
For each of the 18 pins triggering can be done based on rise edge, fall edge, any edge, high or low. | For each of the 18 pins triggering can be done based on rise edge, fall edge, any edge, high or low. | ||
- | ==== Register Map ==== | ||
- | |< 100% 5% 5% 5% 25% 5% 55% >| | + | ===== Register Map ===== |
- | |Address ||Bits |Name |Type |Description | | + | |
- | |DWORD |BYTE |::: |::: |::: |::: | | + | |< 100% 5% 5% 5% 25% 5% 5% 50% >| |
- | ^0x0000 ^0x0000 ^REG_VERSION ^^^Version Register ^ | + | |Address ||Bits |Name |Type |Default |
- | | | |[31:0] |VERSION |RO |Version number | | + | |DWORD |BYTE |::: |::: |::: |::: |::: | |
- | ^0x0001 ^0x0004 ^REG_SCRATCH ^^^Scratch Register ^ | + | ^0x0000 ^0x0000 ^REG_VERSION |
- | | | |[31:0] |SCRATCH |RW |Scratch register | | + | | | |[31:0] |VERSION |RO |0x00 |Version number | |
- | ^0x0002 ^0x0008 ^REG_DIVIDER_COUNTER_LA ^^^Downsampling Counter ^ | + | ^0x0001 ^0x0004 ^REG_SCRATCH |
- | | | |[31:0] |DIVIDER_COUNTER |RW |Register used for down sampling the logic analyzer data. Sample data every (divider_counter + 1) samples | | + | | | |[31:0] |SCRATCH |RW |0x00 |Scratch register | |
- | ^0x0003 ^0x000c ^REG_DIVIDER_COUNTER_PG ^^^Upsampling Counter | + | ^0x0002 ^0x0008 ^REG_DIVIDER_COUNTER_LA |
- | | | |[31:0] |DIVIDER_COUNTER |RW |Register used for upsampling pattern generator data. Sample data every (divider counter + 1) samples | | + | | | |[31:0] |DIVIDER_COUNTER |RW |0x00 |Register used for down sampling the logic analyzer data. Sample data every (divider_counter + 1) samples | |
- | ^0x0004 ^0x0010 ^REG_IO_SELECTION ^^^Data Pins Direction ^ | + | ^0x0003 ^0x000c ^REG_DIVIDER_COUNTER_PG |
- | | | |[15:0] |DIRECTION |RW |Selects which pins are inputs(1) and which are outputs (0). Each bit configures the corresponding pin | | + | | | |[31:0] |DIVIDER_COUNTER |RW |0x00 |Register used for upsampling pattern generator data. Sample data every (divider counter + 1) samples | |
- | ^0x0005 ^0x0014 ^REG_EDGE_DETECT_CONTROL ^^^Any Edge Triggering ^ | + | ^0x0004 ^0x0010 ^REG_IO_SELECTION |
- | | | |[17:16] |TRIGGER[1: | + | | | |[15:0] |DIRECTION |RW |0x00 |Selects which pins are inputs(1) and which are outputs (0). Each bit configures the corresponding pin | |
- | |::: |::: |[15:0] |DATA |RW |Enables any edge detection triggering based on the data pins | | + | ^0x0005 ^0x0014 ^REG_EDGE_DETECT_CONTROL |
- | ^0x0006 ^0x0018 ^REG_RISE_EDGE_CONTROL ^^^Rise Edge Triggering ^ | + | | | |[17:16] |TRIGGER[1: |
- | | | |[17:16] |TRIGGER[1: | + | |::: |::: |[15:0] |DATA |RW |0x00 |Enables any edge detection triggering based on the data pins | |
- | |::: |::: |[15:0] |DATA[15:0] |RW |Enables rise edge detection triggering based on the data pins | | + | ^0x0006 ^0x0018 ^REG_RISE_EDGE_CONTROL |
- | ^0x0007 ^0x001c ^REG_FALL_EDGE_CONTROL ^^^Fall Edge Triggering ^ | + | | | |[17:16] |TRIGGER[1: |
- | | | |[17:16] |TRIGGER[1: | + | |::: |::: |[15:0] |DATA[15:0] |RW |0x00 |Enables rise edge detection triggering based on the data pins | |
- | |::: |::: |[15:0] |DATA[15:0] |RW |Enables fall edge detection triggering based on the data pins | | + | ^0x0007 ^0x001c ^REG_FALL_EDGE_CONTROL |
- | ^0x0008 ^0x0020 ^REG_LOW_LEVEL_CONTROL ^^^Low Level Triggering ^ | + | | | |[17:16] |TRIGGER[1: |
- | | | |[17:16] |TRIGGER[1: | + | |::: |::: |[15:0] |DATA[15:0] |RW |0x00 |Enables fall edge detection triggering based on the data pins | |
- | |::: |::: |[15:0] |DATA[15:0] |RW |Enables low level triggering based on the data pins | | + | ^0x0008 ^0x0020 ^REG_LOW_LEVEL_CONTROL |
- | ^0x0009 ^0x0024 ^REG_HIGH_LEVEL_CONTROL ^^^High Level Triggering ^ | + | | | |[17:16] |TRIGGER[1: |
- | | | |[17:16] |TRIGGER[1: | + | |::: |::: |[15:0] |DATA[15:0] |RW |0x00 |Enables low level triggering based on the data pins | |
- | |::: |::: |[15:0] |DATA[15:0] |RW |Enables high level triggering based on the data pins | | + | ^0x0009 ^0x0024 ^REG_HIGH_LEVEL_CONTROL |
- | ^0x000A ^0x0028 ^REG_TRIGGER_DELAY | + | | | |[17:16] |TRIGGER[1: |
- | | | |[31:0] |TRIGGER_DELAY | + | |::: |::: |[15:0] |DATA[15:0] |RW |0x00 |Enables high level triggering based on the data pins | |
- | ^0x000B ^0x002c ^REG_TRIGGER_LOGIC ^^^Trigger Mix ^ | + | ^0x000A ^0x0028 ^REG_FIFO_DEPTH |
- | | | |[0] |TRIGGER_LOGIC |RW |Combines the enable triggers through an OR (0) or an AND (1) gate | | + | | | |[31:0] |FIFO_DEPTH |
- | ^0x000C ^0x0030 ^REG_CLOCK_SELECT ^^^Clock Selection Multiplexer ^ | + | ^0x000B ^0x002c ^REG_TRIGGER_LOGIC |
- | | | |[0] |CLOCK_SELECT |RW |Selects between clk(0) and data[0] (1) as clock for the logic analyzer and pattern generator paths | | + | | | |[6:4] |TRIGGER_MUX_OUT |RW |0x00 |Final Trigger Selection Multiplexer \\ Selects triggers: \\ 0: TRIGGER_LOGIC \\ 1: TRIGGER_ADC\\ |
- | ^0x000D ^0x0034 ^REG_OVERWRITE_MASK ^^^Overwrite data_o Value ^ | + | |::: |::: |[0] |TRIGGER_LOGIC |RW |0x00 |Combines the enable triggers through an OR (0) or an AND (1) gate | |
- | | | |[15:0] |OVERWRITE_MASK |RW |If set to 1, the specific data_o pin will be driven by the value written in the REG_OVERWRITE_DATA register, instead of the DMA | | + | ^0x000C ^0x0030 ^REG_CLOCK_SELECT |
- | ^0x000E ^0x0038 ^REG_OVERWRITE_DATA ^^^Overwrite Value For data_o ^ | + | | | |[0] |CLOCK_SELECT |RW |0x00 |Selects between clk(0) and data[0] (1) as clock for the logic analyzer and pattern generator paths | |
- | | | |[15:0] |OVERWRITE_DATA |RW |Overwrite value to drive data_o directly, when the mask is applied | | + | ^0x000D ^0x0034 ^REG_OVERWRITE_MASK |
- | ^0x000F ^0x003c ^REG_INPUT_DATA ^^^Read the values | + | | | |[15:0] |OVERWRITE_MASK |RW |0x00 |If set to 1, the specific data_o pin will be driven by the value written in the REG_OVERWRITE_DATA register, instead of the DMA | |
- | | | |[15:0] |INPUT_DATA |RO |The value of the input data, synchronized | | + | ^0x000E ^0x0038 ^REG_OVERWRITE_DATA |
- | ^0x0010 ^0x0040 ^REG_OUTPUT_MODE ^^^Controls | + | | | |[15:0] |OVERWRITE_DATA |RW |
- | | | |[0] |OUTPUT_MODE |RW |Data output is in push-pull (0) or open-drain(1) mode | | + | ^0x000F ^0x003c ^REG_INPUT_DATA |
+ | | | |[15:0] |INPUT_DATA |RO |0x00 |The value of the input data, synchronized | | ||
+ | ^0x0010 ^0x0040 ^REG_OUTPUT_MODE | ||
+ | | | |[0] |OUTPUT_MODE |RW |0x00 |Data output is in push-pull (0) or open-drain(1) mode | | ||
+ | ^0x0011 ^0x0044 ^REG_TRIGGER_DELAY ^^^^Control the Trigger Delay ^ | ||
+ | | | |[31:0] |TRIGGER_DELAY |RW |0x00 |Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger | | ||
+ | ^0x0012 ^0x0048 ^REG_TRIGGERED ^^^^Indicates Triggering Status ^ | ||
+ | | | |[0] |TRIGGERED |RW1C |0x00 |Indicates if the trigger has been triggered since the last time this register has been reset. | | ||
+ | ^0x0013 ^0x004c ^REG_STREAMING ^^^^Controls Streaming Mode ^ | ||
+ | | | |[0] |STREAMING |RW |0x00 |If the streaming bit is set, after the trigger condition is met data will be continuosly | ||
+ | ^0x0014 ^0x0050 ^REG_TRIGGER_HOLDOFF ^^^^Controls the Trigger hold off time ^ | ||
+ | | | |[31:0] |TRIGGER_HOLDOFF |RW |0x00 |Defines the time interval, after a trigger event, where the next trigger events will be ignored, until the end of the interval. The time interval is set by counter. Down-counting on the ADC clock(100MHz)/ | ||
+ | ^0x0015 ^0x0054 ^REG_PG_TRIGGER_CONFIG ^^^^Pattern generator trigger configuration ^ | ||
+ | | | |[19] |EN_TRIGGER_LA |RW |0x00 |Enable trigger from Logic Analyzer | | ||
+ | |::: |::: |[18] |EN_TRIGGER_ADC |RW |0x00 |Enable trigger from ADC | | ||
+ | |::: |::: |[17] |EN_TRIGGER_TO |RW |0x00 |Enable trigger from To | | ||
+ | |::: |::: |[16] |EN_TRIGGER_TI |RW |0x00 |Enable trigger from Ti | | ||
+ | |::: |::: |[9:8] |HIGH_LEVEL |RW |0x00 |High level triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin | | ||
+ | |::: |::: |[7:6] |LOW_LEVEL |RW |0x00 |Low level triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin | | ||
+ | |::: |::: |[5:4] |FALL_EDGE |RW |0x00 |Falling edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin | | ||
+ | |::: |::: |[3:2] |RISE_EDGE |RW |0x00 |Rising edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin | | ||
+ | |::: |::: |[1:0] |ANY_EDGE |RW |0x00 |Any edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin | | ||
+ | ^0x0014 ^0x0050 ^REG_DATA_DELAY_CONTROL ^^^^Controls the synchronization to ADC data ^ | ||
+ | | | |[9] |MASTER_DELAY_CTRL |RW |0x00 |Select if the number of delay taps is chosen by the user(=1) or automatically(=0). Default is 0 or automatically | | ||
+ | |::: |::: |[8] |RATE_GEN_SELECT |RW |0x00 |Selects if the rate is generated by the logic analyzer(0) or it comes from the ADC(1). Default is 0 or logic analyzer | | ||
+ | |::: |::: |[5:0] |MANUAL_DATA_DELAY |RW |0x00 |If MASTER_DELAY_CTRL is set to user delay, the data will be delayed with a number of samples specified it the MANUAL_DATA_DELAY field | | ||
+ | ^Fri Sep 4 12:22:13 2020 ^^^^^^ | ||
+ | |||
+ | |||
+ | ===== References ===== | ||
- | ==== References ==== | + | |
- | | + | * [[/ |
- | * [[https:// | + | * [[https:// |
- | * [[https:// | + | * [[xilinx>support/ |
- | * [[http://www.xilinx.com/support/ | + | * [[xilinx>support/ |
- | * [[http://www.xilinx.com/support/ | + | * [[xilinx>support/ |
- | * [[http://www.xilinx.com/support/ | + | |
- | {{navigation #axi_ip|AXI IP#hdl|Main page#tips|Tips}} | + | {{navigation |