The most recent version of this page is a draft.DiffThis version (11 Oct 2021 15:54) was approved by Adrian Costina.The Previously approved version (10 Feb 2021 10:42) is available.Diff

This is an old revision of the document!


The axi_hdmi_tx IP core can be used to interface the ADV7511 device using an FPGA.


  • AXI based configuration
  • Supports multiple resolution (max 1080p)
  • Video transmission on 36, 24 and 16 bits
  • Supports embedded sync (16bit data)
  • YCbCr or RGB color space output
  • Data clipping (min. and max. for each chroma/color value)
  • Supports Xilinx 7 Series and Ultrascale devices.
  • Supports Altera 5 Series SoC

Block Diagram

Configuration Parameters

Name Description Default Value
ID Core ID should be unique for each axi_hdmi_tx IP in the system 0
DEVICE_TYPE Used to select between Xilinx-7 Series (0) or Xilinx-Ultrascale (1) ALTERA 5 series (16) devices 0
CR_CB_N Used in the chroma subsampling process, selecting which of the red or blue data components will be transmitted first in-between green samples. 1 = red, 0 = blue 0
INTERFACE Interface type towards the 7511. Available options: 16_BIT, 24_BIT, 36_BIT, 16_BIT_EMBEDDED_SYNC 16_BIT
OUT_CLK_POLARITY 0 = Launch on rising edge, 1 = Launch on falling edge 0


Interface Pin Type Description
HDMI common interfaces part HDMI interface signals (LVCMOS)
hdmi_clk input pixel clock, generated by an axi_clkgen IP core (axi_hdmi_clkgen in reference design)
hdmi_out_clk output output clock
16-bit interface HDMI 16-bit data interface signals (LVCMOS)
hdmi_16_hsync output horizontal sync signal
hdmi_16_vsync output vertical sync signal
hdmi_16_data_e output data enable signal
hdmi_16_data output [15:0] hdmi data
16-bit ES interface HDMI 16-bit data Embedded Sync interface signals (LVCMOS)
hdmi_16_es_data output [15:0] hdmi embedded sync data
24-bit interface HDMI 24-bit data interface signals (LVCMOS)
hdmi_24_hsync output horizontal sync signal
hdmi_24_vsync output vertical sync signal
hdmi_24_data_e output data enable signal
hdmi_24_data output [23:0] hdmi data
36-bit interface HDMI 36-bit data interface signals (LVCMOS)
hdmi_36_hsync output horizontal sync signal
hdmi_36_vsync output vertical sync signal
hdmi_36_data_e output data enable signal
hdmi_36_data output [35:0] hdmi data
DMA AXIS interface DMA interface
vdma_clk input DMA clock signal
vdma_end_of_frame input AXIS TLAST signal. End of frame indicator.
vdma_valid input AXIS TVALID signal. Data enable signal.
vdma_data input [63:0] AXIS TDATA signal.
vdma_ready output AXIS TREADY signal.
s_axi AXI Memory Map interface

Detailed description

The top module (axi_hdmi_tx), instantiates:

  • axi_hdmi_tx_core module
  • axi_hdmi_tx_vdma module
  • the HDMI TX register map
  • the AXI handling interface

In axi_hdmi_tx_core module the video information is manipulated by passing through several processing blocks (see Block Diagram):

  • CSC (Color Space Converter) –converts the video information from RGB color space to YCbCr color space. If RGB is the desired output color space the CSC block can be bypassed by setting to 1 the value of CSC_BYPASS register.
  • Data Clipping bloc gives the possibility of limiting the minimum and maximum color range values. This block is controlled by FULL_RANGE, REG_CLIPP_MAX and REG_CLIPP_MIN registers.
  • Chroma subsampling block as its name suggests, samples the video information to obtain a video information that requires less bandwidth and has a minimum impact on the video quality experienced by human eyes.
  • Embedded Sync module interleaves the video synchronization signals with the video information, obtaining a more compact transmission path.
  • Sync Signals block is responsible for generating the video synchronization signals for video resolutions written in HDMI interface Control register.

The axi_hdmi_tx_vdma module ensures the clock domain crossing circuit between the video source, typically a DMAC core and the axi_hdmi_core, which works at different clock speeds depending on the required resolution.

Register Map

HDMI Transmit (axi_hdmi_tx)

Click to expand regmap

Design considerations

Additional IPs needed:

  • axi_dmac
  • axi_clkgen
  • axi_spdif_tx

High-Speed DMA Controller Peripheral (axi_dmac) provides a high-bandwidth direct memory access for the video stream. The core is configured as follows:

ad_ip_instance axi_dmac axi_hdmi_dma
ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_hdmi_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_hdmi_dma CONFIG.CYCLIC true
ad_ip_parameter axi_hdmi_dma CONFIG.DMA_2D_TRANSFER true
ad_ip_parameter axi_hdmi_dma CONFIG.DMA_DATA_WIDTH_DEST 64
The audio path is separated from the video path, for audio axi_spdif_tx core (axi_spdif_tx) is needed to transmit the audio information to the ADV7511 device. The whole system needs to be controlled by a processor (ARM or a soft core) that can programs the registers.
Axi_clkgen generates the clock frequency required for the desired resolution (pixel clock), the frequency is software configurable ( Example adv7511_zc706 no-Os software).

Examples for different data width configurations

The ADV7511 can accept video data from as few as eight pins (either YCbCr 4:2:2 double data rate [DDR] or YCbCr 4:2:2 with 2x pixel clock) to as many as 36 pins (RGB 4:4:4 or YCbCr 4:4:4). In addition it can accept HSYNC, VSYNC and DE (Data Enable)

The axi_hdmi_tx core support the following video input connections:

  • 36 bits with HSYNC, VSYNC and DE (VC707 development board)
  • 24 bits with HSYNC, VSYNC and DE (ZC706 development board)
  • 16 bits with HSYNC, VSYNC and DE (ZedBoard)
  • 16 bits with embedded SYNC (TX interface of the IMAGEON board)

Software support

The core can be controlled by no-Os or Linux


/srv/ · Last modified: 30 Jan 2023 09:09 by Joyce Velasco