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This version (11 Oct 2021 15:53) was approved by Adrian Costina.The Previously approved version (09 Feb 2021 18:54) is available.

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AXI_HDMI_RX IP core

The axi_hdmi_rx IP core can be used to interface the ADV7611 device using an FPGA.

Features

AXI based configuration
Supports multiple resolution (max 1080p)
Supports embedded sync video reception (16bit data)
YCbCr or RGB color space output
Supported on FMC-IMAGEON Xilinx Reference Design

Block Diagram

Configuration Parameters

Name	Description	Default Value
`ID`	Core ID should be unique for each axi_hdmi_rx IP in the system	0
`IO_INTERFACE`	Type of the IO interface. 0 - Allow sampling of data on falling edge of the HDMI clock. others - always sample the input data on rising edge	1

Interfaces

Interface	Pin	Type	Description
`HDMI interfaces part`	HDMI interface signals
	`hdmi_clk`	`input`	pixel clock
	`hdmi_rx_data`	`input [15:0]`	hdmi data
`DMA interface`	DMA Write FIFO interface
	`hdmi_clk`	`output`	Output clock signal
	`hdmi_dma_sof`	`output`	start of frame
	`hdmi_dma_de`	`output`	data enable
	`hdmi_dma_data`	`output [63:0]`	HDMI DMA data
	`hdmi_dma_ovf`	`input`	data overflow signal
	`hdmi_dma_unf`	`input`	data underflow signal
`s_ axi`	AXI Memory Map interface

Detailed description

The top module, axi_hdmi_rx, instantiates:

axi_hdmi_rx_core module
the HDMI RX register map
the AXI handling interface

In axi_hdmi_rx_core module, the video information is manipulated by passing through more processing blocks (see Block Diagram):

Embedded Sync module acquires the video information and splits it into video data and synchronization signals.
Chroma supersampling block, super samples the video information to obtain a 24 bit video information, has no impact on the video quality.
CSC (Color Space Conversion) –converts the video information from YCbCr color space to RGB color space. If YCbCr is the desired output color space the CSC block can be bypassed by setting to 1 the value of CSC_BYPASS in REG_CNTRL register.
Sync monitoring - monitors the recovered hsync and vsync against the programmed expected resolution. Asserts out of sync and resoulutions mismatch indicators in the REG_TPM_STATUS2 regsiter.

Register Map

HDMI Receive (axi_hdmi_rx)

Click to expand regmap

0x0010	0x0040	REG_RSTN				HDMI Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[0]	RSTN	RW	0x0	Reset, a common reset is used for all the interface modules, The default is reset (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL				HDMI Interface Control & Status
		[3]	EDGE_SEL	RW	0x0	If set (0x1), incoming data is registered on the falling edge of the clock first. The default uses rising edge.
		[2]	BGR	RW	0x0	If set (0x1), output BGR. The default is RGB.
		[1]	PACKED	RW	0x0	If set (0x1) pack 24bit RGB data on 32bit dwords. The default pads the MSB to zeros.
		[0]	CSC_BYPASS	RW	0x0	If set (0x1) bypasses color space conversion (if equipped).
0x0015	0x0054	REG_CLK_FREQ				HDMI Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO				HDMI Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0018	0x0060	REG_VDMA_STATUS				HDMI Interface Control & Status
		[1]	VDMA_OVF	RW1C	0x0	If set, indicates vdma overflow.
		[0]	VDMA_UNF	RW1C	0x0	If set, indicates vdma underflow.
0x0019	0x0064	REG_TPM_STATUS1				HDMI Interface Control & Status
		[1]	HDMI_TPM_OOS	RW1C	0x0	If set, indicates TPM OOS at the HDMI interface.
0x0020	0x0080	REG_TPM_STATUS2				HDMI Interface Control & Status
		[3]	VS_OOS	RW1C	0x0	If set, indicates VSYNC OOS - the core is unabled to detect/track VSYNC. Consecutive frames have different number of lines.
		[2]	HS_OOS	RW1C	0x0	If set, indicates HSYNC OOS - the core is unabled to detect/track HSYNC. Consecutive lines have different lengths.
		[1]	VS_MISMATCH	RW1C	0x0	If set, indicates received (detected) & programmed VSYNC (number of lines) mismatch. Incoming frames are stable but not the expected resolution.
		[0]	HS_MISMATCH	RW1C	0x0	If set, indicates received (detected) & programmed HSYNC (number of pixels) mismatch. Incoming frames are stable but not the expected resolution.
0x0100	0x0400	REG_HVCOUNTS1				HDMI Interface Control & Status
		[31:16]	VS_COUNT[15:0]	RW	0x0000	This is the expected active horizontal pixel lines (active resolution length). e.g. 1080 (1080p)
		[15:0]	HS_COUNT[15:0]	RW	0x0000	This is the expected horizontal pixel count (no. of pixel clocks per line). e.g. 1920 (1080p)
0x0101	0x0404	REG_HVCOUNTS2				HDMI Interface Control & Status
		[31:16]	VS_COUNT[15:0]	RO	0x0000	This is the detected horizontal active pixel lines (active resolution length). This field is valid only if VS_OOS is zero.
		[15:0]	HS_COUNT[15:0]	RO	0x0000	This is the detected horizontal pixel count (no. of pixel clocks per line). This field is valid only if HS_OOS is zero.
Tue Mar 14 10:17:59 2023

Design considerations

Additional IPs needed:

axi_dmac
axi_spdif_tx (audio)

The axi_dmac is used to get the video information from the core into memory. The audio path is separated from the video path, for audio axi_spdif_tx core (axi_spdif_tx) is needed to receive the audio information from the ADV7611 device and transmit it to the memory. The whole system needs to be controlled by a processor (ARM or a softcore) that can program the registers.

Example design

The core is used to interface the ADV7611 located on the FMC IMAGEON board. Although the device support multiple pixel output formats, the core is supporting just the 16-bit 4:2:2 in SDR mode.

IMAGEON HDL project

Software support

The core can be controlled by Linux or no-Os

References

Prev.: AXI IP coresUp: Main pageNext.: Using and modifying the HDL design

Wiki

Analog Devices Wiki

Table of Contents

AXI_HDMI_RX IP core

Features

Block Diagram

Configuration Parameters

Interfaces

Detailed description

Register Map

HDMI Receive (axi_hdmi_rx)

Design considerations

Additional IPs needed:

Example design

Software support

References

Analog Devices Wiki

Table of Contents

AXI_HDMI_RX IP core

Features

Block Diagram

Configuration Parameters

Interfaces

Detailed description

Register Map

HDMI Receive (axi_hdmi_rx)

Design considerations

Additional IPs needed:

Example design

Software support

References

Page Tools