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| ||Core ID should be unique for each axi_hdmi_rx IP in the system||0|
| ||Type of the IO interface. 0 - Allow sampling of data on falling edge of the HDMI clock. others - always sample the input data on rising edge||1|
| ||HDMI interface signals|
| || ||pixel clock|
| || ||hdmi data|
| ||DMA Write FIFO interface|
| || ||Output clock signal|
| || ||start of frame|
| || ||data enable|
| || ||HDMI DMA data|
| || ||data overflow signal|
| || ||data underflow signal|
| ||AXI Memory Map interface|
The top module, axi_hdmi_rx, instantiates:
In axi_hdmi_rx_core module, the video information is manipulated by passing through more processing blocks (see Block Diagram):
The axi_dmac is used to get the video information from the core into memory.
The audio path is separated from the video path, for audio axi_spdif_tx core (axi_spdif_tx) is needed to receive the audio information from the ADV7611 device and transmit it to the memory.
The whole system needs to be controlled by a processor (ARM or a softcore) that can program the registers.
The core is used to interface the ADV7611 located on the FMC IMAGEON board. Although the device support multiple pixel output formats, the core is supporting just the 16-bit 4:2:2 in SDR mode.