The most recent version of this page is a draft.DiffThis version (11 Oct 2021 15:53) was approved by Adrian Costina.The Previously approved version (09 Feb 2021 18:54) is available.Diff

This is an old revision of the document!


The axi_hdmi_rx IP core can be used to interface the ADV7611 device using an FPGA.


  • AXI based configuration
  • Supports multiple resolution (max 1080p)
  • Supports embedded sync video reception (16bit data)
  • YCbCr or RGB color space output
  • Supported on FMC-IMAGEON Xilinx Reference Design

Block Diagram

Configuration Parameters

Name Description Default Value
​ID Core ID should be unique for each axi_hdmi_rx IP in the system 0
IO_INTERFACE Type of the IO interface. 0 - Allow sampling of data on falling edge of the HDMI clock. others - always sample the input data on rising edge 1


Interface Pin Type Description
HDMI interfaces part HDMI interface signals
hdmi_clk input pixel clock
hdmi_rx_data input [15:0] hdmi data
DMA interface DMA Write FIFO interface
hdmi_clk output Output clock signal
hdmi_dma_sof output start of frame
hdmi_dma_de output data enable
hdmi_dma_data output [63:0] HDMI DMA data
hdmi_dma_ovf input data overflow signal
hdmi_dma_unf input data underflow signal
s_ axi AXI Memory Map interface

Detailed description

The top module, axi_hdmi_rx, instantiates:

  • axi_hdmi_rx_core module
  • the HDMI RX register map
  • the AXI handling interface

In axi_hdmi_rx_core module, the video information is manipulated by passing through more processing blocks (see Block Diagram):

  • Embedded Sync module acquires the video information and splits it into video data and synchronization signals.
  • Chroma supersampling block, super samples the video information to obtain a 24 bit video information, has no impact on the video quality.
  • CSC (Color Space Conversion) –converts the video information from YCbCr color space to RGB color space. If YCbCr is the desired output color space the CSC block can be bypassed by setting to 1 the value of CSC_BYPASS in REG_CNTRL register.
  • Sync monitoring - monitors the recovered hsync and vsync against the programmed expected resolution. Asserts out of sync and resoulutions mismatch indicators in the REG_TPM_STATUS2 regsiter.

Register Map

HDMI Receive (axi_hdmi_rx)

Click to expand regmap

Design considerations

Additional IPs needed:

The axi_dmac is used to get the video information from the core into memory. The audio path is separated from the video path, for audio axi_spdif_tx core (axi_spdif_tx) is needed to receive the audio information from the ADV7611 device and transmit it to the memory. The whole system needs to be controlled by a processor (ARM or a softcore) that can program the registers.

Example design

The core is used to interface the ADV7611 located on the FMC IMAGEON board. Although the device support multiple pixel output formats, the core is supporting just the 16-bit 4:2:2 in SDR mode.

Software support

The core can be controlled by Linux or no-Os


/srv/ · Last modified: 30 Jan 2023 09:04 by Joyce Velasco