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resources:fpga:docs:axi_fan_control [27 Mar 2019 10:39] – added temp parameters, sergiu arpadi | resources:fpga:docs:axi_fan_control [12 Oct 2021 16:50] (current) – Edit title & cosmetic changes Iulia Moldovan | ||
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- | + | ====== | |
- | ====== Fan Control IP Core ====== | + | |
- | The [[https:// | + | The [[https:// |
+ | Its purpose is to control the fan used for the cooling of a Xilinx Zynq Ultrascale+ MPSoC without the need of any external temperature sensors. \\ | ||
+ | To achieve this, the IP core uses the PL SYSMONE4 primitive to obtain the PL temperature via the DRP interface. Based on the temperature readings it then outputs a PWM signal to control the fan rotation accordingly. The tacho signal coming from the fan is also measured and evaluated to ensure that the RPM is correct and the fan is working properly. | ||
+ | ===== Block Diagram ===== | ||
- | ==== Block Diagram ==== | ||
{{: | {{: | ||
- | |||
- | ====== Introduction ====== | ||
- | The purpose of this IP core is to control the fan used for the cooling of a Xilinx Zynq Ultrascale+ MPSoC without the need of any external temperature sensors. To achieve this, the IP core uses the PL SYSMONE4 primitive to obtain the PL temperature via the DRP interface. Based on the temperature readings it then outputs a PWM signal to control the fan rotation accordingly. The tacho signal coming from the fan is also measured and evaluated to ensure that the RPM is correct and the fan is working properly. | ||
+ | ===== Configuration Parameters ===== | ||
- | ==== Configuration Parameter ==== | ||
^ Name ^ Description ^ Default Value^ | ^ Name ^ Description ^ Default Value^ | ||
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+ | | '' | ||
- | ==== Signal and Interface Pins ==== | + | ===== Signal and Interface Pins ===== |
^ Interface ^ Pin ^ Type ^ Description ^ | ^ Interface ^ Pin ^ Type ^ Description ^ | ||
| | '' | | | '' | ||
| | '' | | | '' | ||
- | | | '' | + | | | '' |
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| | '' | | | '' | ||
- | ==== Register Map ==== | + | ===== Clocking ===== |
- | {{page>: | + | |
- | ==== Clocking ==== | ||
The IP core runs on the AXI clock and requires a frequency of 100MHz. | The IP core runs on the AXI clock and requires a frequency of 100MHz. | ||
- | ==== Theory of Operation ==== | + | ===== Theory of Operation ===== |
- | The main features of this IP core are its independent operation and the fact that it does not require an external temperature sensor. All of the mechanisms contained inside the core are controlled by a state machine, so that they do not depend on the software in case the software fails. The state machine uses the temperature it reads from the SYSMONE4 primitive to decide the correct PWM duty-cycle. The temperature thresholds and hysteresis are defined in the hardware and cannot be modified by the software. | + | |
+ | The main features of this IP core are its independent operation and the fact that it does not require an external temperature sensor. All of the mechanisms contained inside the core are controlled by a state machine, so that they do not depend on the software in case the software fails. The state machine uses the temperature it reads from the SYSMONE4 primitive or via the " | ||
- | === Running independently === | + | |
- | The hardware can operate with minimal | + | ==== Running independently |
+ | The hardware can operate with no input from the software; the IP core starts | ||
There are 9 temperature intervals defined in the hardware as below: | There are 9 temperature intervals defined in the hardware as below: | ||
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{{ : | {{ : | ||
- | Five of these intervals have only one possible duty-cycle and four of them can have either of the neighbouring values. After reset the PWM duty-cycle will start as 100%. The state-machine will begin reading the temperature | + | Five of these intervals have only one possible duty-cycle and four of them can have either of the neighbouring values. After reset the PWM duty-cycle will start as 100%. The state-machine will begin reading the temperature and will decide on the PWM duty cycle depending on which interval the value matches. The PWM duty-cycle will only change when the temperature enters one of the five intervals with a single PWM duty-cycle, in the other four the previous duty-cycle will be maintained. In these intervals its value will depend on whether the temperature is rising or falling. The temperature can be reconfigured by the software. |
- | The temperature is obtained from the PL SYSMONE4 primitive | + | The temperature is obtained from the PL SYSMONE4 primitive |
+ | //Internal SYSMONE4 primitive: // | ||
// | // | ||
- | [[https:// | + | [[xilinx>support/ |
+ | |||
+ | //Reading from temp_in: // | ||
+ | // | ||
There are five configurations described in the hardware, each with a corresponding tacho period +/- 25% tolerance. | There are five configurations described in the hardware, each with a corresponding tacho period +/- 25% tolerance. | ||
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- | === Software control and customization === | + | ==== Software control and customization |
- | The software can request | + | |
+ | The software can overwrite the temperature thresholds and the tacho values if needed. The TEMP_00_H -> TEMP_100_L registers can redefine the temperature intervals and the TACHO_25 -> TACHO_100 registers can also be used to redefine tacho values if a different | ||
+ | |||
+ | The software can also set a custom | ||
//i.e. 5KHz -> 20000 * 10 ns = 200 us// | //i.e. 5KHz -> 20000 * 10 ns = 200 us// | ||
- | The software may request a different PWM duty-cycle if needed by writing to the PWM_WIDTH register. | + | The new PWM value must be greater or equal to the value selected by the hardware and less or equal to the PWM period. The software can use the PWM_WIDTH and PWM_PERIOD registers in order to make sure the new value is valid. |
After requesting a new duty-cycle there is a 5 second delay during which the hardware waits for the fan rotaion speed to stabilize. The software will then have to provide parameters for the tacho signal in order for the hardware to be able to evaluate it. To do this the software will have to write the TACHO_PERIOD and TACHO_TOLERANCE registers in that order. The software can read the TACHO_MEASUREMENT register to obtain the new tacho period and derive the tolerance value from it. | After requesting a new duty-cycle there is a 5 second delay during which the hardware waits for the fan rotaion speed to stabilize. The software will then have to provide parameters for the tacho signal in order for the hardware to be able to evaluate it. To do this the software will have to write the TACHO_PERIOD and TACHO_TOLERANCE registers in that order. The software can read the TACHO_MEASUREMENT register to obtain the new tacho period and derive the tolerance value from it. | ||
- | A mearsurement is performed by averaging | + | A mearsurement is performed by averaging |
The software can now use this register to read the new tacho pediod and then write it to the TACHO_PERIOD register. Then it can write a tolerance value to the TACHO_TOLERANCE register. The hardware will only start to monitor the tacho signal when the tolerance is provided. | The software can now use this register to read the new tacho pediod and then write it to the TACHO_PERIOD register. Then it can write a tolerance value to the TACHO_TOLERANCE register. The hardware will only start to monitor the tacho signal when the tolerance is provided. | ||
- | === Interrupts === | + | ==== Interrupts ==== |
The fan controller supports interrupts to both inform the software of any possible errors and also to facilitate the control of the core. There are four interrupt sources: | The fan controller supports interrupts to both inform the software of any possible errors and also to facilitate the control of the core. There are four interrupt sources: | ||
*The '' | *The '' | ||
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*The '' | *The '' | ||
+ | |||
+ | ===== Register Map ===== | ||
+ | |||
+ | {{page>: | ||
+ | |||
+ | {{navigation HDL User Guide# |