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resources:fpga:docs:axi_dac_ip [11 Oct 2021 15:05] – Edit next page to be Using and modifying the HDL design Iulia Moldovanresources:fpga:docs:axi_dac_ip [13 Oct 2021 10:17] (current) – Edit footer & cosmetic updates Iulia Moldovan
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 <note important>Any kind of feedback regarding the DAC IP architecture or the following document is highly appreciated and can be addressed through the [[ez>community/fpga|FPGA Reference Designs]] community forum.</note>    <note important>Any kind of feedback regarding the DAC IP architecture or the following document is highly appreciated and can be addressed through the [[ez>community/fpga|FPGA Reference Designs]] community forum.</note>   
 +
  
 ===== Architecture ===== ===== Architecture =====
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   * Data source multiplexer   * Data source multiplexer
   * IQ correction module   * IQ correction module
- 
-TODO: wiki page about each module 
-TODO: describe the (Read) FIFO interface 
  
 ==== DAC core ==== ==== DAC core ====
  
 The DAC core is the top file of the IP core, the naming convention of this file is: axi_<device_name>.v . Here are instantiated all the internal module discussed above, and a wrapper module (up_axi), which converts the AXI interface into a more simplistic addressable, memory mapped interface, so called [[resources:fpga:docs:up_if|microprocessor interface]] or uP interface. This interface is used to interconnect the different memory mapped module pieces. The DAC core is the top file of the IP core, the naming convention of this file is: axi_<device_name>.v . Here are instantiated all the internal module discussed above, and a wrapper module (up_axi), which converts the AXI interface into a more simplistic addressable, memory mapped interface, so called [[resources:fpga:docs:up_if|microprocessor interface]] or uP interface. This interface is used to interconnect the different memory mapped module pieces.
 +
  
 ===== Signal and Interface Pins ===== ===== Signal and Interface Pins =====
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 |** AXI Memory Map Slave ** |||| |** AXI Memory Map Slave ** ||||
 |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface for register map access | |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface for register map access |
-===== Register Map ===== 
  
-TODO: wiki page about the register map architecture  + 
-  * present the AXI Memory Mapped interface +===== Register Map =====
-  * talk about the UP_AXI wrapper and the simplified register interface +
-  * present read and write logic +
-  * present CDC circuits+
  
 The following block diagram presents the different register maps physical location in the core. These register maps are generic and can be found in each AXI DAC core. The following block diagram presents the different register maps physical location in the core. These register maps are generic and can be found in each AXI DAC core.
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 {{page>:resources:fpga:docs:hdl:regmap##IO Delay Control (axi_ad*)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##IO Delay Control (axi_ad*)&nofooter&noeditbtn}}
  
-==== References ====+ 
 +===== References =====
   * [[resources:fpga:docs:axi_ad9361|AXI_AD9361 IP Description]]   * [[resources:fpga:docs:axi_ad9361|AXI_AD9361 IP Description]]
  
-{{navigation HDL User Guide#axi_ip|AXI IP cores#hdl|Main page#tips|Using and modifying the HDL design}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_dac_ip.txt · Last modified: 13 Oct 2021 10:17 by Iulia Moldovan

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