This version is outdated by a newer approved version.
This version (25 May 2017 10:42) is a draft.
Approvals: 0/1
This version (25 May 2017 10:42) is a draft.Approvals: 0/1
This is an old revision of the document!
Table of Contents
AXI_DAC_INTERPOLATE
The AXI_DAC_INTERPOLATE IP allows interpolation of the input data by 10/100/1000/10000/100000, with filtering and arbitrary zero-hold interpolation.
Features
- AXI Lite control/status interface
- Allows interpolation by 10/100/1000/10000/100000 with filtering
- Allows arbitrary zero-hold interpolation
- Filtering is implemented by a 6 sections CIC programmable rate filter and a compensation FIR filter.
- Controls the data flow so that multiple channels can be synchronized
Block Diagram
Interface
| Interface | Pin | Type | Description |
|---|---|---|---|
| Clock | |||
dac_clk | input | Clock input | |
| Reset | |||
dac_rst | input | Reset, synchronous on the dac_clk clock domain | |
| Data Inputs | |||
dac_data_a | input[15:0] | Analog data for channel A | |
dac_data_b | input[15:0] | Analog data for channel B | |
dac_data_valid_a | input | Data valid signal for channel A | |
dac_data_valid_b | input | Data valid signal for channel B | |
| Interpolated Outputs | |||
dac_int_data_a | output[15:0] | Interpolated data for channel A | |
dac_int_data_b | output[15:0] | Interpolated data for channel B | |
dac_int_valid_a | output | Data valid for channel A | |
dac_int_valid_b | output | Data valid for channel B | |
| AXI_S_MM interface | |||
s_axi_* | Standard AXI Slave Memory Map interface | ||
Detailed Description
For some applications the maximum sampling rate of the DAC is too high and leads to a bad utilization of the memory or USB bandwidth. In order to avoid that, the interpolation IP can be used. The interpolation block allows interpolation by 10, 100, 1000, 10000,100000 with filtering. The filtering is implemented using a FIR compensation filter (interpolation by 2) for the CIC and a 6 stage CIC interpolation filter allowing interpolation by 5/50/500/5000/50000. At the end of the filter blocks, there is an arbitrary interpolation zero-order hold block which holds the value for a configurable number of samples.
Register Map
| Address | Bits | Name | Type | Description | |
| DWORD | BYTE | ||||
| 0x0000 | 0x0000 | REG_VERSION | Version Register | ||
|---|---|---|---|---|---|
| [31:0] | VERSION[31:0] | RO | Version number | ||
| 0x0001 | 0x0004 | REG_SCRATCH | Scratch Register | ||
| [31:0] | ID[31:0] | RW | Scratch register | ||
| 0x0010 | 0x0040 | REG_ARBITRARY_INTERPOLATION_RATIO_A | Control Arbitrary Interpolation Ratio | ||
| [31:0] | INTERPOLATION_RATIO | RW | Set the arbitrary zero-order hold interpolation ratio at the end of the interpolation chain | ||
| 0x0011 | 0x0044 | REG_FILTERED_INTERPOLATION_RATIO_A | Enable Filtered Interpolation. | ||
| [2:0] | INTERPOLATION_RATIO | RW | Enables the filtered interpolation: 0: No filtered interpolation 1: Interpolation by 10. Result should be corrected by a 1.531 factor 2: Interpolation by 100. Result should be corrected by a 1.168 factor 3: Interpolation by 1000. Result should be corrected by a 1.783 factor 6: Interpolation by 10000. Result should be corrected by a 1.360 factor 7: Interpolation by 100000. Result should be corrected by a 1.038 factor default: No filtered interpolation |
||
| 0x0012 | 0x0048 | REG_ARBITRARY_INTERPOLATION_RATIO_B | Control Arbitrary Interpolation Ratio | ||
| [31:0] | INTERPOLATION_RATIO | RW | Set the arbitrary zero-order hold interpolation ratio at the end of the interpolation chain | ||
| 0x0013 | 0x004c | REG_FILTERED_INTERPOLATION_RATIO_B | Enable Filtered Interpolation | ||
| [2:0] | INTERPOLATION_RATIO | RW | Enables the filtered interpolation: 0: No filtered interpolation 1: Interpolation by 10. Result should be corrected by a 1.531 factor 2: Interpolation by 100. Result should be corrected by a 1.168 factor 3: Interpolation by 1000. Result should be corrected by a 1.783 factor 6: Interpolation by 10000. Result should be corrected by a 1.360 factor 7: Interpolation by 100000. Result should be corrected by a 1.038 factor default: No filtered interpolation |
||
| 0x0014 | 0x0050 | REG_FLAGS | Control Flags | ||
| [0] | SUSPEND_TRANSFER | RW | If set to 1, the interpolation filters are in reset and no data is requested from the DMA. Can be used to synchronize data transfer from two different DMAs. | ||
References
Navigation -
resources/fpga/docs/axi_dac_interpolate.1495701752.txt.gz · Last modified: 25 May 2017 10:42 by Adrian Costina