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The most recent version of this page is a draft.DiffThis version (11 Oct 2021 16:02) was approved by Adrian Costina.The Previously approved version (09 Jan 2021 00:39) is available.Diff

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Table of Contents

AXI_DAC_INTERPOLATE

The AXI_DAC_INTERPOLATE IP allows interpolation of the input data by 10/100/1000/10000/100000, with filtering and arbitrary zero-hold interpolation.

Features

  • AXI Lite control/status interface
  • Allows interpolation by 10/100/1000/10000/100000 with filtering
  • Allows arbitrary zero-hold interpolation
  • Filtering is implemented by a 6 sections CIC programmable rate filter and a compensation FIR filter.
  • Controls the data flow so that multiple channels can be synchronized

Block Diagram

AXI_DAC_INTERPOLATE Block diagram

Configuration Parameters

Name Description Default Value
CORRECTION_DISABLE Disable scale correction of the CIC output 1

Interface

Interface Pin Type Description
Clock
dac_clk input Clock input
Reset
dac_rst input Reset, synchronous on the dac_clk clock domain
Data Inputs
dac_data_a input[15:0] Analog data for channel A
dac_data_b input[15:0] Analog data for channel B
dac_data_valid_a input Data valid signal for channel A
dac_data_valid_b input Data valid signal for channel B
Interpolated Outputs
dac_int_data_a output[15:0] Interpolated data for channel A
dac_int_data_b output[15:0] Interpolated data for channel B
dac_int_valid_a output Data valid for channel A
dac_int_valid_b output Data valid for channel B
Trigger input
trigger_i input[1:0] External trigger pins
trigger_adc input ADC trigger
trigger_la input Logic Analyzer trigget
AXI_S_MM interface
s_axi_* Standard AXI Slave Memory Map interface

Detailed Description

For some applications, the maximum sampling rate of the DAC is too high and leads to a bad utilization of the memory or USB bandwidth. In order to avoid that, the interpolation IP can be used.

The interpolation block allows interpolation by 10, 100, 1000, 10000,100000 with filtering. The filtering is implemented using an FIR compensation filter (interpolation by 2) for the CIC and a 6 stage CIC interpolation filter allowing interpolation by 5/50/500/5000/50000.

At the end of the filter blocks, there is an arbitrary interpolation zero-order hold block which holds the value for a configurable number of samples.

Register Map

Address Bits Name Type Default Description
DWORD BYTE
0x0000 0x0000 REG_VERSION Version Register
[31:0] VERSION RO 0x00 Version number
0x0001 0x0004 REG_SCRATCH Scratch Register
[31:0] SCRATCH RW 0x00 Scratch register
0x0010 0x0040 REG_ARBITRARY_INTERPOLATION_RATIO_A Control Arbitrary Interpolation Ratio for Channel A
[31:0] FILTERED_INTERPOLATION RW 0x00 Set the arbitrary zero-order hold interpolation ratio at the end of the interpolation chain
0x0011 0x0044 REG_INTERPOLATION_RATIO_A Control Filtered Interpolation for Channel A
[2:0] FILTERED_INTERPOLATION RW 0x00 Enables the filtered interpolation:
0: No filtered interpolation
1: Interpolation by 10. Result should be corrected by a 1.531 factor
2: Interpolation by 100. Result should be corrected by a 1.168 factor
3: Interpolation by 1000. Result should be corrected by a 1.783 factor
6: Interpolation by 10000. Result should be corrected by a 1.360 factor
7: Interpolation by 100000. Result should be corrected by a 1.038 factor
default: No filtered interpolation
0x0012 0x0048 REG_ARBITRARY_INTERPOLATION_RATIO_B Control Arbitrary Interpolation Ratio for Channel B
[31:0] FILTERED_INTERPOLATION RW 0x00 Set the arbitrary zero-order hold interpolation ratio at the end of the interpolation chain
0x0013 0x004c REG_INTERPOLATION_RATIO_B Control Filtered Interpolation for Channel B
[2:0] FILTERED_INTERPOLATION RW 0x00 Enables the filtered interpolation:
0: No filtered interpolation
1: Interpolation by 10. Result should be corrected by a 1.531 factor
2: Interpolation by 100. Result should be corrected by a 1.168 factor
3: Interpolation by 1000. Result should be corrected by a 1.783 factor
6: Interpolation by 10000. Result should be corrected by a 1.360 factor
7: Interpolation by 100000. Result should be corrected by a 1.038 factor
default: No filtered interpolation
0x0014 0x0050 REG_FLAGS Control Flags
[0] SUSPEND_TRANSFER RW 0x00 If set to 1, the interpolation filters are in reset and no data is requested from the DMA. Can be used to synchronize data transfer from two different DMAs.
0x0015 0x0054 REG_CONFIG Configuration Register
[1] CORRECTION_ENABLE_B RW 0x00 If set to 1, correction is enabled on channel B. The input data will be multiplied with the value from the CORRECTION_COEFFICIENT_B register.
[0] CORRECTION_ENABLE_A RW 0x00 If set to 1, correction is enabled on channel A. The input data will be multiplied with the value from the CORRECTION_COEFFICIENT_A register.
0x0016 0x0058 REG_CORRECTION_COEFFICIENT_A Correction Coefficient A
[15:0] CORRECTION_COEFFICIENT RW 0x00 Scale correction (if equipped) coefficient for channel A. The format is 1.1.14 (sign, integer and fractional bits). Allows for correction of the CIC filter amplification.
0x0017 0x005c REG_CORRECTION_COEFFICIENT_B Correction Coefficient B
[15:0] CORRECTION_COEFFICIENT RW 0x00 Scale correction (if equipped) coefficient for channel B. The format is 1.1.14 (sign, integer and fractional bits). Allows for correction of the CIC filter amplification.
0x0018 0x0060 REG_TRIGGER_CONFIG Trigger configuration
[19] EN_TRIGGER_LA RW 0x00 Enable trigger from Logic Analyzer
[18] EN_TRIGGER_ADC RW 0x00 Enable trigger from ADC
[17] EN_TRIGGER_TO RW 0x00 Enable trigger from To
[16] EN_TRIGGER_TI RW 0x00 Enable trigger from Ti
[9:8] FALL_EDGE RW 0x00 Falling edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
[7:6] RISE_EDGE RW 0x00 Rising edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
[5:4]] ANY_EDGE RW 0x00 Any edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
[3:2] HIGH_LEVEL RW 0x00 High level triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
[1:0] LOW_LEVEL RW 0x00 Low level triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin
Fri Sep 4 17:18:13 2020

References

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