Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
resources:fpga:docs:axi_clkgen [12 Oct 2021 13:11] – Edit footer to point to IP cores Iulia Moldovanresources:fpga:docs:axi_clkgen [12 Oct 2021 16:45] (current) – Edit title Iulia Moldovan
Line 1: Line 1:
-====== AXI_CLKGEN IP core ======+====== AXI CLKGEN IP core ======
  
 The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_clkgen|axi_clkgen]] IP core is a software programmable clock generator. The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_clkgen|axi_clkgen]] IP core is a software programmable clock generator.
 +
  
 ===== Block Diagram ===== ===== Block Diagram =====
Line 13: Line 14:
  
 The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface. The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface.
 +
  
 ===== Configuration Parameters ===== ===== Configuration Parameters =====
Line 27: Line 29:
 | ''CLK1_DIV'' | CLKOUT1_DIVIDE MMCM parameter | 6 | | ''CLK1_DIV'' | CLKOUT1_DIVIDE MMCM parameter | 6 |
 | ''CLK1_PHASE'' | CLKOUT1_PHASE MMCM parameter | 0.000 | | ''CLK1_PHASE'' | CLKOUT1_PHASE MMCM parameter | 0.000 |
 +
  
 ===== Signal and Interface Pins ===== ===== Signal and Interface Pins =====
Line 37: Line 40:
 |                 | ''clk_1'' | ''output'' | Output clock 1 | |                 | ''clk_1'' | ''output'' | Output clock 1 |
 | ''s_axi '' | **AXI Slave Memory Map interface** ||| | ''s_axi '' | **AXI Slave Memory Map interface** |||
 +
  
 ===== Register Map ===== ===== Register Map =====
 +
 {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}}
 {{page>:resources:fpga:docs:hdl:regmap##Clock Generator (axi_clkgen)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##Clock Generator (axi_clkgen)&nofooter&noeditbtn}}
 +
  
 ===== References ===== ===== References =====
resources/fpga/docs/axi_clkgen.1634037069.txt.gz · Last modified: 12 Oct 2021 13:11 by Iulia Moldovan

Page Tools