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resources:fpga:docs:axi_clkgen [07 Jul 2017 13:20] – Fix link to landing page Istvan Csomortaniresources:fpga:docs:axi_clkgen [12 Oct 2021 16:45] (current) – Edit title Iulia Moldovan
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-===== AXI_CLKGEN IP core =====+====== AXI CLKGEN IP core ======
  
 The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_clkgen|axi_clkgen]] IP core is a software programmable clock generator. The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_clkgen|axi_clkgen]] IP core is a software programmable clock generator.
  
-==== Block Diagram ==== 
  
-{{  :resources:fpga:docs:axi_clkgen.png | AXI_CLKGEN Block diagram }}+===== Block Diagram ===== 
 + 
 +{{  :resources:fpga:docs:axi_clkgen_1.svg | AXI_CLKGEN Block diagram }}
  
 \\ \\
-The top module, axi_clkgen, instantiates a mmcm wrapper, the CLKGEN register map and the AXI handling interface.+The top module, axi_clkgen, instantiates a [[https://github.com/analogdevicesinc/hdl/blob/hdl_2016_r2/library/xilinx/common/ad_mmcm_drp.v|mcm wrapper]], the [[resources:fpga:docs:hdl:regmap#clock_generator_axi_clkgen|CLKGEN register map]] and the [[resources:fpga:docs:up_if|AXI handling]] interface.
  
-The ad_mmcm_drp is a wrapper over MMCM, which can instantiate a Virtex 6 MMCM or 7 Series MMCM. Detailed information regarding the 7 Series MMCM can be found in Xilinx UG472 and UG953.+The ad_mmcm_drp is a wrapper over MMCM, which can instantiate a Virtex 6 MMCM or 7 Series MMCM. Detailed information regarding the 7 Series MMCM can be found in Xilinx [[xilinx>support/documentation/user_guides/ug472_7Series_Clocking.pdf|UG472]] and [[xilinx>support/documentation/sw_manuals/xilinx2015_2/ug953-vivado-7series-libraries.pdf|UG953]].
  
 The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface. The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface.
  
-==== Configuration Parameter ====+ 
 +===== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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 | ''CLK1_DIV'' | CLKOUT1_DIVIDE MMCM parameter | 6 | | ''CLK1_DIV'' | CLKOUT1_DIVIDE MMCM parameter | 6 |
 | ''CLK1_PHASE'' | CLKOUT1_PHASE MMCM parameter | 0.000 | | ''CLK1_PHASE'' | CLKOUT1_PHASE MMCM parameter | 0.000 |
-| ''CLK2_DIV'' | CLKOUT2_DIVIDE MMCM paramter| 6 | 
-| ''CLK2_PHASE'' | CLKOUT2_PHASE MMCM parameter | 0.000 | 
  
-==== Signal and Interface Pins ====+ 
 +===== Signal and Interface Pins =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
-| '' Clocks'' | **Input and output clocks** ||| +| '' Clocks''     | **Input and output clocks** ||| 
-|              | ''clk'' | ''input'' | Reference clock 1 | +|                 | ''clk'' | ''input'' | Reference clock 1 | 
-|              | ''clk2'' | ''input'' | Reference clock 2 | +|                 | ''clk2'' | ''input'' | Reference clock 2 | 
-|              | ''clk_0'' | ''output'' | Output clock 0 | +|                 | ''clk_0'' | ''output'' | Output clock 0 | 
-|              | ''clk_1'' | ''output'' | Output clock 1 | +|                 | ''clk_1'' | ''output'' | Output clock 1 | 
-| ''s axi '' | **AXI Slave Memory Map interface** |||+| ''s_axi '' | **AXI Slave Memory Map interface** ||| 
 + 
 + 
 +===== Register Map =====
  
-==== Register Map ==== 
 {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}}
 {{page>:resources:fpga:docs:hdl:regmap##Clock Generator (axi_clkgen)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##Clock Generator (axi_clkgen)&nofooter&noeditbtn}}
  
-{{navigation #axi_ip|AXI IP#hdl|Main page#util_ip|UTIL IP Cores}} 
  
 +===== References =====
 +
 +  * [[xilinx>support/documentation/user_guides/ug472_7Series_Clocking.pdf|7 Series FPGAs Clocking Resources User Guide]]
 +  * [[xilinx>support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf|MMCM and PLL Dynamic Reconfiguration]]
  
 +{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_clkgen.1499426456.txt.gz · Last modified: 07 Jul 2017 13:20 by Istvan Csomortani

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