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AXI_ADXCVR

The AXI_ADXCVR is a utility core used to control and configure the highspeed transceivers instantiated in UTIL_ADXCVR. There are separate AXI_ADXCVR cores for Intel and Xilinx designs, due to the small differences between the Xilinx's and Intel's transceivers architecture.

Features

Supports Intel and Xilinx devices.
Software can access the core's registers through an AXI4 Lite Memory Mapped interface.
Link reset and monitor for Intel and Xilinx.
Reconfiguration interface control with broadcast capability for Xilinx.
Access to the Statistical eye scan interface of the PHY (Xilinx).
Supports up to 16 transceiver lanes per link. (Xilinx)

Intel Devices

For Intel devices, the adi_jesd204 IP is using the axi_adxcvr core, which can be accessed by the link_management interface. It provides a global reset signal for the JESD204B framework. Resets the XCVR reset controller IP, the link PLL reset controller, the PHY itself, and also the link layer of the stack. Besides the reset generation, monitors the PLLs and the PHY state.

Parameters

Name	Description	Default Value
`ID`	Instance identification number, if more than one instance is used.	0
`NUM_OF_LANES`	The number of lanes (primitives) used in this link.	8
`XCVR_TYPE`	Refers to the transciver speed grade 0-9.	0
`FPGA_TECHNOLOGY`	Encoded value describing the technology/generation of the FPGA device (e.g., Cyclone V, Arria 10, Stratix 10)	0
`FPGA_FAMILY`	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT)	0
`SPEED_GRADE`	Encoded value describing the FPGA's speed-grade	0
`DEV_PACKAGE`	Encoded value describing the device package. The package might affect high-speed interfaces	0
`FPGA_VOLTAGE`	Contains the value(0-5000 mV) at wich the FPGA device supplied	0
`TX_OR_RX_N`	If set (0x1), configures the link in transmit mode, otherwise receive.	0

Interface	Pin	Type	Description
`axi_aclk`	`axi_aclk`	Input	System clock. (in general 100 MHz)
`axi_aresetn`	`axi_aresetn`	Input	System reset.
`s_axi`	Slave-AXI	IO	Slave AXI4 Lite Memory Mapped interface
`up_pll_locked`	`core_pll_locked`	Input	Connect to the fPLL's pll_locked pin.
`up_ready`	`ready`	Input	Connect to PHY reset controller.

Register Map

0x0000	0x0000	REG_VERSION			Version Register
Address		Bits	Name	Type	Description
DWORD	BYTE	Bits	Name	Type	Description
		[31:0]	VERSION[31:0]	RO	Version number.
0x0001	0x0004	REG_ID			Instance Identification Register
		[31:0]	ID[31:0]	RO	Instance identifier number.
0x0002	0x0008	REG_SCRATCH			Scratch (GP R/W) Register
		[31:0]	SCRATCH[31:0]	RW	Scratch register.
0x0004	0x0010	REG_RESETN			Reset Control Register
		[0]	RESETN	RW	If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock must be active before setting this bit.
0x0005	0x0014	REG_STATUS			Status Reporting Register
		[0]	STATUS	RO	After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
0x0006	0x0018	REG_STATUS_32			Status Reporting Register
		[31:NUM_OF_LANES]	RESERVED	RO	0
		[NUM_OF_LANES]	UP_PLL_LOCKED	RO	After setting the RESETN bit above, wait for this bit be to set.
		[NUM_OF_LANES-1:0]	CHANNEL_N_READY	RO	After setting the RESETN bit above, wait for this registers to be set.
0x0007	0x001c	REG_FPGA_INFO			FPGA device information Intel encoded values
		[31:24]	FPGA_TECHNOLOGY	RO	Encoded value describing the technology/generation of the FPGA device (e.g., cyclone V, arria 10, stratix 10)
		[23:16]	FPGA_FAMILY	RO	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
		[15:8]	SPEED_GRADE	RO	Encoded value describing the FPGA's speed-grade
		[7:0]	DEV_PACKAGE	RO	Encoded value describing the device package. The package might affect high-speed interfaces
0x0009	0x0024	REG_GENERIC_INFO			Physical layer info
		[31:28]	RESERVED	RO	0
		[27:24]	XCVR_TYPE[3:0]	RO	Refers to the transceiver speed grade 0-9.
		[23:12]	RESERVED	RO	0
		[11:9]	RESERVED	RO	0
		[8]	TX_OR_RX_N	RO	Transceiver type (transmit or receive)
		[7:0]	NUM_OF_LANES	RO	Physical layer number of lanes.
0x0050	0x0140	REG_FPGA_VOLTAGE			FPGA device voltage information
		[15:0]	FPGA_VOLTAGE	RO	The voltage of the FPGA device in mv

Software Guidelines

When the board powers up, both ATX and fPLL's must have a stable reference clock in order to lock automatically. If this requirement can not be respected by the system (e.g. the reference clocks are generated by a device that requires software configuration, through an interface implemented in FPGA), the software needs to reconfigure both PLLs, and just after that resets the transceivers.

Xilinx Devices

In Xilinx Devices, the core configures itself to be interfaced with the GT variant supported by the UTIL_ADXCVR core. All the transceiver primitives are configured and programmed identically.

Parameters

Name	Description	Default Value
`ID`	Instance identification number, if more than one instance is used.	0
`NUM_OF_LANES`	The number of lanes (primitives) used in this link.	8
`XCVR_TYPE`	Define the current GT type, GTXE2(2), GTHE3(5), GTHE4(7).	0
`FPGA_TECHNOLOGY`	Encoded value describing the technology/generation of the FPGA device (7series/ultrascale)	0
`FPGA_FAMILY`	Encoded value describing the family variant of the FPGA device(e.g., zynq, kintex, virtex)	0
`SPEED_GRADE`	Encoded value describing the FPGA's speed-grade	0
`DEV_PACKAGE`	Encoded value describing the device package. The package might affect high-speed interfaces	0
`FPGA_VOLTAGE`	Contains the value(0-5000 mV) at wich the FPGA device supplied	0
`TX_OR_RX_N`	If set (0x1), configures the link in transmit mode, otherwise receive.	0
`QPLL_ENABLE`	If set (0x1), configures the link to use QPLL on QUAD basis. If multiple links are sharing the same transceiver, only one of them may enable the QPLL.	1
`LPM_OR_DFE_N`	Chosing between LPM or DFE of modes for the RX Equalizer	1
`RATE`	Defines the initial values for Transceiver Control Register (REG_CONTROL 0x0008)	0
`TX_DIFFCTRL`	Driver Swing Control(TX Configurable Driver)	8
`TX_POSTCURSOR`	Transmitter post-cursor TX pre-emphasis control.	0
`TX_PRECURSOR`	Transmitter pre-cursor TX pre-emphasis control.	0
`SYS_CLK_SEL`	Selects the PLL reference clock source to drive the RXOUTCLK Table 1	3
`OUT_CLK_SEL`	select the transceiver reference clock as the source of TXOUTCLK Table 2	4

Interface

Interface	Pin	Type	Description
`axi_clk`	`axi_clk`	Input	The CPU clock (assumed to be 100MHz), must be same as the DRP clock.
`axi_aresetn`	`axi_aresetn`	Input	The CPU reset (internally used asynchronous to the axi_clk).
`up_status`	`up_status`	Output	If set, indicates that the link is up and active. The same information is read on the register bit (see below). This signal may be connected to the JESD204B IP reset done input.
`s_axi`	Slave-AXI	IO	The programmable interface, must be connected to a CPU master.
`m_axi`	Master-AXI	IO	The Eye-Scan DMA interface, must be connected to a memory slave. This interface is available only if parameter TX_OR_RX_N is set to 0x0.
`up_cm_*`	Common-DRP	IO	The common DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a QUAD interface, shared by four transceiver lanes. This interface is available only if parameter QPLL_ENABLE is set to 0x1.
`up_ch_*`	Channel-DRP	IO	The channel DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane.
`up_es_*`	Eye-Scan-DRP	IO	The Eye-Scan DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane. This interface is available only if parameter TX_OR_RX_N is set to 0x0.

Register Map

Xilinx XCVR (axi_xcvr) Regmap

Click to expand regmap

0x0000	0x0000	VERSION				Version Register
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION	RO	0x00	Version number.
0x0001	0x0004	ID				Instance Identification Register
		[31:0]	ID	RO	0x00	Instance identifier number.
0x0002	0x0008	SCRATCH				Scratch (GP R/W) Register
		[31:0]	SCRATCH	RW	0x00	Scratch register.
0x0004	0x0010	RESETN				Reset Control Register
		[1]	BUFSTATUS_RST	RW	0x00	Initially this flag is held in reset with value 0x1, in order for a user to see the RX BUFSTATUS, this flag needs to be set to 0x0.
		[0]	RESETN	RW	0x00	If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock and DRP clock must be active before setting this bit.
0x0005	0x0014	STATUS				Status Reporting Register
		[6:5]	BUFSTATUS	RO	0x00	BUFSTATUS provides status for either the RX buffer or the TX buffer. If BUFSTATUS is referring to the TX buffer, once BUFSTATUS is set High it remains High until RESETN is activated. Else if BUFSTATUS is referring to the RX buffer, once BUFSTSTATUS is High it can be cleared using BUFSTATUS_RST. If BUFTATUS[6] is 0x1 the internal FIFO overflows and when the BUFSTATUS[5] is 0x1 the internal FIFO underflows. Available from version 17.5.a. For more information consult the transceiver user guide(search for RXBUFSTATUS/TXBUFSTATUS).
		[4]	PLL_LOCK_N	RO	0x00	After setting the RESETN bit above, this bit must clear. If does not clears, indicates the CPLL/QPLL did not locked. Available from version 17.4.a
		[0]	STATUS	RO	0x00	After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
0x0007	0x001c	FPGA_INFO				FPGA device information Xilinx encoded values
		[31:24]	FPGA_TECHNOLOGY	RO	0x00	Encoded value describing the technology/generation of the FPGA device (e.g, 7series, ultrascale)
		[23:16]	FPGA_FAMILY	RO	0x00	Encoded value describing the family variant of the FPGA device(e.g., zynq, kintex, virtex)
		[15:8]	SPEED_GRADE	RO	0x00	Encoded value describing the FPGA's speed-grade
		[7:0]	DEV_PACKAGE	RO	0x00	Encoded value describing the device package. The package might affect high-speed interfaces
0x0008	0x0020	CONTROL				Transceiver Control Register
		[12]	LPM_DFE_N	RW	0x00	Transceiver primitive control, refer Xilinx documentation.
		[10:8]	RATE[2:0]	RW	0x00	Transceiver primitive control, refer Xilinx documentation.
		[5:4]	SYSCLK_SEL[1:0]	RW	0x00	For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver. Refer to Xilinx documentation. For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see Table 1.
		[2:0]	OUTCLK_SEL[2:0]	RW	0x00	Transceiver primitive control Table 2, refer Xilinx documentation.
0x0009	0x0024	GENERIC_INFO				Physical layer info
		[20]	QPLL_ENABLE	RO	0x00	Using QPLL.
		[19:16]	XCVR_TYPE[3:0]	RO	0x00	Xilinx encoded values.
		[13:12]	LINK_MODE	RO	0x00	Link layer mode : 01 - 8B10B decoder (aka 204B) 10 - 64B66B decoder (aka 204C); Available from version 17.3.a
		[8]	TX_OR_RX_N	RO	0x00	Transceiver type (transmit or receive)
		[7:0]	NUM_OF_LANES	RO	0x00	Physical layer number of lanes.
0x0010	0x0040	CM_SEL				Transceiver Access Register
		[7:0]	CM_SEL	RW	0x00	Transceiver common-DRP sel, set to 0xff for broadcast.
0x0011	0x0044	CM_CONTROL				Transceiver Access Register
		[28]	CM_WR	RW	0x00	Transceiver common-DRP sel, set to 0x1 for write, 0x0 for read.
		[27:16]	CM_ADDR	RW	0x00	Transceiver common-DRP read/write address.
		[15:0]	CM_WDATA	RW	0x00	Transceiver common-DRP write data.
0x0012	0x0048	CM_STATUS				Transceiver Access Register
		[16]	CM_BUSY	RO	0x00	Transceiver common-DRP access busy (0x1) or idle (0x0).
		[15:0]	CM_RDATA	RW	0x00	Transceiver common-DRP read data.
0x0018	0x0060	CH_SEL				Transceiver Access Register
		[7:0]	CH_SEL	RW	0x00	Transceiver channel-DRP sel, set to 0xff for broadcast.
0x0019	0x0064	CH_CONTROL				Transceiver Access Register
		[28]	CH_WR	RW	0x00	Transceiver channel-DRP sel, set to 0x1 for write, 0x0 for read.
		[27:16]	CH_ADDR	RW	0x00	Transceiver channel-DRP read/write address.
		[15:0]	CH_WDATA	RW	0x00	Transceiver channel-DRP write data.
0x001a	0x0068	CH_STATUS				Transceiver Access Register
		[16]	CH_BUSY	RO	0x00	Transceiver channel-DRP access busy (0x1) or idle (0x0).
		[15:0]	CH_RDATA	RW	0x00	Transceiver channel-DRP read data.
0x0020	0x0080	ES_SEL				Transceiver Access Register
		[7:0]	ES_SEL	RW	0x00	Transceiver eye-scan-DRP sel, set to 0xff for broadcast.
0x0028	0x00a0	ES_REQ				Transceiver eye-scan Request Register
		[0]	ES_REQ	RW	0x00	Transceiver eye-scan request, set this bit to initiate an eye-scan, this bit auto-clears when scan is complete.
0x0029	0x00a4	ES_CONTROL_1				Transceiver eye-scan Control Register
		[4:0]	ES_PRESCALE[4:0]	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
0x002a	0x00a8	0x00a8				ES_CONTROL_2 Transceiver eye-scan Control Register
		[25:24]	ES_VOFFSET_RANGE	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
		[23:16]	ES_VOFFSET_STEP	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
		[15:8]	ES_VOFFSET_MAX	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
		[7:0]	ES_VOFFSET_MIN	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
0x002b	0x00ac	ES_CONTROL_3				Transceiver eye-scan Control Register
		[27:16]	ES_HOFFSET_MAX	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
		[11:0]	ES_HOFFSET_MIN	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
0x002c	0x00b0	ES_CONTROL_4				Transceiver eye-scan Control Register
		[11:0]	ES_HOFFSET_STEP	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
0x002d	0x00b4	ES_CONTROL_5				Transceiver eye-scan Control Register
		[31:0]	ES_STARTADDR	RW	0x00	Transceiver eye-scan control, DMA start address (ES data is written to this memory address).
0x002e	0x00b8	ES_STATUS				Transceiver eye-scan Status Register
		[0]	ES_STATUS	RO	0x00	If set, indicates an error in ES DMA.
0x002F	0x00bc	ES_RESET				Transceiver eye-scan reset control register
		[n]	ES_RESET	RW	0x00	Controls the EYESCANRESET pin of the GTH/GTY transceivers for lane n.
0x0030	0x00c0	TX_DIFFCTRL				Transceiver primitive control, refer Xilinx documentation.
		[31:0]	TX_DIFFCTRL	RW	0x00	TX driver swing control.
0x0031	0x00c4	TX_POSTCURSOR				Transceiver primitive control, refer Xilinx documentation.
		[31:0]	TX_POSTCURSOR	RW	0x00	Transmiter post-cursor TX pre-emphasis control.
0x0032	0x00c8	TX_PRECURSOR				Transceiver primitive control, refer Xilinx documentation.
		[31:0]	TX_PRECURSOR	RW	0x00	Transmiter pre-cursor TX pre-emphasis control.
0x0050	0x0140	FPGA_VOLTAGE				FPGA device voltage information
		[15:0]	FPGA_VOLTAGE	RO	0x00	The voltage of the FPGA device in mv
0x0060	0x0180	PRBS_CNTRL				Transceiver PRBS control
		[16]	PRBSFORCEERR	RW	0x00	Valid for TX. If set, a single error is forced in the PRBS transmitter for every clock cycle. Can be used to test the PRBS checkers on the other side of the link.
		[8]	PRBSCNTRESET	RW	0x00	Valid for RX. Resets the PRBS error counter from the transceiver. Does not self clears. Value of error counter must be accessed via DRP.
		[3:0]	PRBSSEL	RW	0x00	PRBS checker or generator test pattern control. All zeros will put the PRBS in bypass mode. For TX non-zero values will stop the normal dataflow from link layer and will inject a pattern instead. See transceiver guide for specific values.
0x0061	0x0184	PRBS_STATUS				RX Transceiver PRBS status
		[8]	PRBSERR	RO	0x00	This sticky status output indicates that PRBS errors have occurred. Value of error counter must be accessed via DRP.
		[0]	PRBSLOCKED	RO	0x00	Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET
Tue Mar 14 10:17:59 2023

Software Guidelines

The system must have active DRP and reference clocks before any software access. The software is expected to write necessary control parameters to LPM_DFE_N, RATE, SYSCLK_SEL, OUTCLK_SEL register bits and then set RESETN bit to 0x1. After which monitor the STATUS bit to be set. There are no other requirements for initialization.

The DRP access is identical for common and channel interfaces. The SEL bits may be set to a specific transceiver lane or 0xff to broadcast. A write to the CONTROL register (bits WR, ADDR, WDATA) initiates DRP access in hardware. A read to this register has no effect. In order to write to the transceiver, set WR to 0x1 with the address. In order to read from the transceiver, set WR to 0x0 with the address. As soon as this register is written, the BUSY signal is set and is cleared only after the access is complete. The broadcast read is a logical OR of all the channels. After an access is started, do NOT interrupt the core for any reason (including setting RESETN to 0x0), allow the access to finish itself. Though the core itself is immune to a software abort, the transceiver may fail on further accesses and may require a system-wide reset.

The eye-scan feature also allows a SEL option and a broadcast has the effect of a combined mask. That is, the error counter will be zero ONLY if all the transceiver error counters are zero. To start eye-scan, set ES_REQ to 0x1 and wait for the same bit to self-clear. If eye-scan needs to be stopped, set the ES_REQ bit to 0x0.

Table 1

SYSCLK_SEL	00	01	10	11
GTXE2	CPLL	RESERVED	RESERVED	QPLL
GTHE3	CPLL	RESERVED	QPLL1	QPLL0
GTHE4	CPLL	RESERVED	QPLL1	QPLL0
GTYE4	CPLL	RESERVED	QPLL1	QPLL0

Table 2

OUTCLK_SEL	001	010	011	100	All other combinations
GTXE2	OUTCLKPCS	OUTCLKPMA	REFCLK	REFCLK/2	RESERVED
GTHE3	OUTCLKPCS	OUTCLKPMA	REFCLK	REFCLK/2	RESERVED
GTHE4	OUTCLKPCS	OUTCLKPMA	REFCLK	REFCLK/2	RESERVED
GTYE4	OUTCLKPCS	OUTCLKPMA	REFCLK	REFCLK/2	RESERVED

The REFCLK selected by OUTCLK_SEL depends on the SYSCLK_SEL, it may be CPLL, QPLL0 or QPLL1 refclk.

Physical layer PRBS testing

The REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.

TX link procedure

Configure ref clock and device clocks for under test lane rate. Bring XCVR out from reset.
In the REG_PRBS_CNTRL registers set PRBSSEL to a non-zero value. See the transceiver guides for exact values, different transceiver families may have different encoding for the same pattern.
On the receiving side of the link set the checker for the same pattern and reset the error counters.
No error should be recorded on the receiver side.
Set the PRBSFORCEERR bit in the REG_PRBS_CNTRL register to force the error injection into the stream of bits.
The error should be detected and recorded on the receiver side.

RX link procedure

Configure ref clock and device clocks for under test lane rate. Bring XCVR out from reset.
On the transmit side of the link set a test pattern that is available in the receiving transceiver. Consult the transceiver documentation for details.
In the REG_PRBS_CNTRL registers set PRBSSEL to the corresponding pattern. Reset the error counters with PRBSCNTRESET.
Check REG_PRBS_STATUS fields for results. If the check is successful for non-GTX transceivers the PRBSLOCKED bit must appear as set and PRBSERR must stay low. For GTX transceivers the PRBSLOCKED bit can be ignored and checking the PRBSERR alone is sufficient. If PRBSERR is set, check with DRP accesses the internal error counter to get the number of errors received. See the transceiver guide for details.

More Information

Reference

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Analog Devices Wiki

Table of Contents

AXI_ADXCVR

Features

Intel Devices

Parameters

Register Map

Software Guidelines

Xilinx Devices

Parameters

Interface

Register Map

Xilinx XCVR (axi_xcvr) Regmap

Software Guidelines

Table 1

Table 2

Physical layer PRBS testing

TX link procedure

RX link procedure

More Information

Reference

Analog Devices Wiki

Table of Contents

AXI_ADXCVR

Features

Intel Devices

Parameters

Register Map

Software Guidelines

Xilinx Devices

Parameters

Interface

Register Map

Xilinx XCVR (axi_xcvr) Regmap

Software Guidelines

Table 1

Table 2

Physical layer PRBS testing

TX link procedure

RX link procedure

More Information

Reference

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