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| Both sides previous revisionPrevious revision | Next revisionBoth sides next revision | ||
| resources:fpga:docs:axi_adxcvr [30 Jan 2019 09:45] – [Register Map] Update with TX driver control registers Istvan Csomortani | resources:fpga:docs:axi_adxcvr [12 Feb 2019 10:07] – Improved SYSCLK_SEL description Adrian Costina | ||
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| Line 60: | Line 60: | ||
| | | |[12] |LPM_DFE_N |RW | Transceiver primitive control, refer Xilinx documentation. | | | | |[12] |LPM_DFE_N |RW | Transceiver primitive control, refer Xilinx documentation. | | ||
| | | |[10:8] |RATE[2:0] |RW | Transceiver primitive control, refer Xilinx documentation. | | | | |[10:8] |RATE[2:0] |RW | Transceiver primitive control, refer Xilinx documentation. | | ||
| - | | | |[5:4] |SYSCLK_SEL[1: | + | | | |[5:4] |SYSCLK_SEL[1: |
| | | |[2:0] |OUTCLK_SEL[2: | | | |[2:0] |OUTCLK_SEL[2: | ||
| ^0x0010 ^0x0040 ^REG_CM_SEL ^^^Transceiver Access Register ^ | ^0x0010 ^0x0040 ^REG_CM_SEL ^^^Transceiver Access Register ^ | ||
resources/fpga/docs/axi_adxcvr.txt · Last modified: 04 Feb 2022 09:11 by Michael Hennerich