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resources:fpga:docs:axi_adc_trigger [11 Oct 2021 14:57] – Edit footer Iulia Moldovanresources:fpga:docs:axi_adc_trigger [13 Oct 2021 09:56] (current) – Edit footer & add reference to generic ADC Iulia Moldovan
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 ====== AXI_ADC_TRIGGER ====== ====== AXI_ADC_TRIGGER ======
  
-The AXI_ADC_TRIGGER IP implements triggering for the ADC path and also controls two I/O triggering pins.+The AXI_ADC_TRIGGER IP implements triggering for the ADC path and also controls two I/O triggering pins.\\ 
 +\\ 
 +More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]]. 
  
 ===== Features ===== ===== Features =====
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   * Instrument trigger (from Logic Analyzer)   * Instrument trigger (from Logic Analyzer)
   * Controls two IO trigger pins   * Controls two IO trigger pins
 +
  
 ===== Block Diagram ===== ===== Block Diagram =====
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 {{:resources:fpga:docs:axi_adc_trigger_diagram.png?600|}} {{:resources:fpga:docs:axi_adc_trigger_diagram.png?600|}}
  
-== AXI ADC Tigger submodules ==+==== AXI ADC Tigger submodules ====
  
   * [[:resources:fpga:docs:axi_adc_trigger#register_map | Register-map ]]   * [[:resources:fpga:docs:axi_adc_trigger#register_map | Register-map ]]
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   * **Holdoff counter** (32 bit) - REG_TRIGGER_HOLDOFF(0x0048) - Controls the trigger out silent period after an event.    * **Holdoff counter** (32 bit) - REG_TRIGGER_HOLDOFF(0x0048) - Controls the trigger out silent period after an event. 
   * **Delay counter** (32 bit) - REG_TRIGGER_DELAY(0x0040) - Controls the trigger delay    * **Delay counter** (32 bit) - REG_TRIGGER_DELAY(0x0040) - Controls the trigger delay 
-* **External trigger control**  + 
-  * REG_IO_SELECTION(0x000c) - Controls the direction of the external trigger pins, and the source(for each pin configured as output) +  * **External trigger control** 
-  * REG_TRIGGER_OUT_HOLD_PINS(0x004c) - Controls the hold period after a transition to a new logic level.+      * REG_IO_SELECTION(0x000c) - Controls the direction of the external trigger pins, and the source(for each pin configured as output) 
 +      * REG_TRIGGER_OUT_HOLD_PINS(0x004c) - Controls the hold period after a transition to a new logic level. 
  
 ===== Interface ===== ===== Interface =====
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 | **AXI_S_MM interface** |||| | **AXI_S_MM interface** ||||
 |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface | |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface |
 +
  
 ===== Detailed Description ===== ===== Detailed Description =====
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 If a history for data before the trigger is needed, a [[:resources:fpga:docs:util_var_fifo | variable FIFO IP ]] should be used. The FIFO depth is controlled using the trigger_offset bus of this IP. If a history for data before the trigger is needed, a [[:resources:fpga:docs:util_var_fifo | variable FIFO IP ]] should be used. The FIFO depth is controlled using the trigger_offset bus of this IP.
 +
  
 ===== Register Map ===== ===== Register Map =====
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 | | |[19:0] |TRIGGER_OUT_HOLD_PINS |RW |0x00 |Defines a time period, in which the external trigger pins, configured as outputs, will hold the new logic level after a transition. The down-counter, counting on ADC clock, is loaded with the value written in the register after a new transition of the source trigger signal, if the counter is inactive. | | | |[19:0] |TRIGGER_OUT_HOLD_PINS |RW |0x00 |Defines a time period, in which the external trigger pins, configured as outputs, will hold the new logic level after a transition. The down-counter, counting on ADC clock, is loaded with the value written in the register after a new transition of the source trigger signal, if the counter is inactive. |
 ^Tue Sep  1 09:58:53 2020 ^^^^^^ ^Tue Sep  1 09:58:53 2020 ^^^^^^
 +
  
 ===== Aditional notes ===== ===== Aditional notes =====
  
 <note important>Instrument triggering in only available from major version 3.</note> <note important>Instrument triggering in only available from major version 3.</note>
 +
  
 ===== References ===== ===== References =====
 +
   * [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_adc_trigger | AXI_ADC_TRIGGER source code]] \\   * [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_adc_trigger | AXI_ADC_TRIGGER source code]] \\
   * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\   * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\
   * [[https://github.com/analogdevicesinc/linux/tree/m2k | ADI Linux repository ]]   * [[https://github.com/analogdevicesinc/linux/tree/m2k | ADI Linux repository ]]
  
-{{navigation HDL User Guide#axi_ip|AXI IP cores#hdl|Main page#tips|Using and modifying the HDL design}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_adc_trigger.txt · Last modified: 13 Oct 2021 09:56 by Iulia Moldovan

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