Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
Next revisionBoth sides next revision
resources:fpga:docs:axi_adc_trigger [19 Aug 2019 17:22] – Adding more info and cosmetics Andrei Grozavresources:fpga:docs:axi_adc_trigger [01 Sep 2020 09:02] – New features, completitions, cosmetics Andrei Grozav
Line 1: Line 1:
-===== AXI_ADC_TRIGGER =====+====== AXI_ADC_TRIGGER ======
  
 The AXI_ADC_TRIGGER IP implements triggering for the ADC path and also controls two I/O triggering pins. The AXI_ADC_TRIGGER IP implements triggering for the ADC path and also controls two I/O triggering pins.
  
-==== Features ====+===== Features =====
  
   * AXI Lite control/status interface   * AXI Lite control/status interface
Line 21: Line 21:
   * Controls two IO trigger pins   * Controls two IO trigger pins
  
-==== Block Diagram ====+===== Block Diagram =====
  
 {{:resources:fpga:docs:axi_adc_trigger_diagram.png?600|}} {{:resources:fpga:docs:axi_adc_trigger_diagram.png?600|}}
Line 28: Line 28:
  
   * [[:resources:fpga:docs:axi_adc_trigger#register_map | Register-map ]]   * [[:resources:fpga:docs:axi_adc_trigger#register_map | Register-map ]]
-  * **IO Selection** - REG_IO_SELECTION(0x000c) - Controles the direction of the external trigger pins, and the source, when the pins configured to output. 
   * **Channel trigger**   * **Channel trigger**
     * Channel A     * Channel A
Line 39: Line 38:
       * Hysteresis - TRIGGER_FUNCTION_A (0x002c) - "+-" value. Used for the passthrough functions       * Hysteresis - TRIGGER_FUNCTION_A (0x002c) - "+-" value. Used for the passthrough functions
  
-<note important>In the case of M2k, the trigger pins(Ti and To) are chosen one for input and one for output. This is for the ease of configuring a daisy-chain of M2k's. The hardware and software support both pins to be configured as in or out</note>+  * **External trigger** 
 +    * Pin 0 (Ti) \\ Configurations - REG_CONFIG_TRIGGER_I(0x004) allows for: 
 +      * falling edge (bit 8) 
 +      * rising edge  (bit 6) 
 +      * any edge     (bit 4) 
 +      * high level   (bit 2) 
 +      * low level    (bit 0) 
 +    * Pin 1 (To) \\ Configurations - REG_CONFIG_TRIGGER_I(0x004) allows for: 
 +      * falling edge (bit 9) 
 +      * rising edge  (bit 7) 
 +      * any edge     (bit 5) 
 +      * high level   (bit 3) 
 +      * low level    (bit 1) 
 + 
 +<note important>In the case of M2k, the trigger pins(Ti and To) are chosen one for input and one for output. This is for the ease of configuring a daisy-chain of M2k's. The hardware and software support both pins to be configured as input or output in REG_IO_SELECTION(0x000c)</note>
    
   * **Channel A MUX** - REG_TRIGGER_MUX_A(0x0020) - Selects between a combination of ADC trigger and the external trigger   * **Channel A MUX** - REG_TRIGGER_MUX_A(0x0020) - Selects between a combination of ADC trigger and the external trigger
   * **Channel B MUX** - REG_TRIGGER_MUX_B(0x0030) - Selects between a combination of ADC trigger and the external trigger   * **Channel B MUX** - REG_TRIGGER_MUX_B(0x0030) - Selects between a combination of ADC trigger and the external trigger
 +
   * **Output MUX** - REG_TRIGGER_OUT_CONTROL(0x0034) - Selects a combination between the channel A and/or B MUX's and the input of the instrument trigger   * **Output MUX** - REG_TRIGGER_OUT_CONTROL(0x0034) - Selects a combination between the channel A and/or B MUX's and the input of the instrument trigger
-  * **Delay counter** (32 bit) - REG_TRIGGER_DELAY(0x0040) - Control the Trigger Delay +  * **Holdoff counter** (32 bit) - REG_TRIGGER_HOLDOFF(0x0048) - Controls the trigger out silent period after an event.  
 +  * **Delay counter** (32 bit) - REG_TRIGGER_DELAY(0x0040) - Controls the trigger delay  
 +* **External trigger control**  
 +  * REG_IO_SELECTION(0x000c) - Controls the direction of the external trigger pins, and the source(for each pin configured as output) 
 +  * REG_TRIGGER_OUT_HOLD_PINS(0x004c) - Controls the hold period after a transition to a new logic level.
  
-==== Interface ====+===== Interface =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
Line 72: Line 90:
 |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface | |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface |
  
-==== Detailed Description ====+===== Detailed Description =====
  
 The AXI_ADC_TRIGGER IP implements triggering for the ADC path. The trigger is generated based on two external trigger pins, a triggering signal from the logic analyzer and the ADC channels. The AXI_ADC_TRIGGER IP implements triggering for the ADC path. The trigger is generated based on two external trigger pins, a triggering signal from the logic analyzer and the ADC channels.
Line 79: Line 97:
  
 The analog triggering is based on comparison with a limit. The data format must be 2's complement and the maximum number of bits of the analog channel is 15. The analog triggering is based on comparison with a limit. The data format must be 2's complement and the maximum number of bits of the analog channel is 15.
-The trigger can be transmitted independent or embedded in the output word, at bit 15. Before forwarding the data to the DMA, the triggers must be extracted and data must be reconstructed. The UTIL_EXTRACT IP can be used for this purpose.+The trigger can be transmitted independent or embedded in the output word, at bit 15. When embedded, the triggers must be extracted and data must be reconstructed, before forwarding the data to the DMA. The UTIL_EXTRACT IP can be used for this purpose.
 Embedding the trigger in the data allows for additional IPs with unknown pipeline length to be introduced in the path. Embedding the trigger in the data allows for additional IPs with unknown pipeline length to be introduced in the path.
  
-If a history for data before the trigger is needed, a variable FIFO IP should be used. The FIFO depth is controlled using the trigger_offset bus of this IP.+If a history for data before the trigger is needed, a [[:resources:fpga:docs:util_var_fifo | variable FIFO IP ]] should be used. The FIFO depth is controlled using the trigger_offset bus of this IP.
  
-==== Register Map ====+===== Register Map =====
  
 |< 100% 5% 5% 5% 25% 5% 5% 50% >| |< 100% 5% 5% 5% 25% 5% 5% 50% >|
Line 97: Line 115:
 |::: |::: |[0] |TRIGGER_O[0] |RW |0x00 |Set TRIGGER_O[0] value | |::: |::: |[0] |TRIGGER_O[0] |RW |0x00 |Set TRIGGER_O[0] value |
 ^0x0003 ^0x000c ^REG_IO_SELECTION ^^^^Control Trigger Pins Direction ^ ^0x0003 ^0x000c ^REG_IO_SELECTION ^^^^Control Trigger Pins Direction ^
-| | |[7:5] |TRIGGER_O[1] (PIN) |RW |0x00 |Select output trigger pin 1 \\   0: SOFTWARE TRIGGER - TRRIGER_O[1](0x0004) \\   1: TRIGGER_I[1] (PIN) \\   2: TRIGGER_I[0] (PIN) \\   3: TRIGGER_OUT (axi_adc_trigger)\\   4: TRIGGER_IN (Logic analyzer) \\ | +| | |[7:5] |TRIGGER_O[1] (To PIN) |RW |0x00 |Select output trigger pin 1 \\   0: SOFTWARE TRIGGER - TRRIGER_O[1](0x0004) \\   1: TRIGGER_I[1] (PIN) \\   2: TRIGGER_I[0] (PIN) \\   3: TRIGGER_OUT (axi_adc_trigger)   4: TRIGGER_IN (Logic analyzer) \\ | 
-|::: |::: |[4:2] |TRIGGER_O[0] (PIN) |RW |0x00 |Select output trigger pin 0 \\   0: SOFTWARE TRIGGER - TRRIGER_O[0](0x0004) \\   1: TRIGGER_I[0] (PIN) \\   2: TRIGGER_I[1] (PIN) \\   3: TRIGGER_OUT (axi_adc_trigger) \\   4: TRIGGER_IN (Logic analyzer) \\ | +|::: |::: |[4:2] |TRIGGER_O[0] (Ti PIN) |RW |0x00 |Select output trigger pin 0 \\   0: SOFTWARE TRIGGER - TRRIGER_O[0](0x0004) \\   1: TRIGGER_I[0] (PIN) \\   2: TRIGGER_I[1] (PIN) \\   3: TRIGGER_OUT (axi_adc_trigger)   4: TRIGGER_IN (Logic analyzer) \\ | 
-|::: |::: |[1] |IO_SELECTION[1] |RW |0x00 |Drives the TRIGGER_T[1] pin | +|::: |::: |[1] |IO_SELECTION[1] |RW |0x00 |Drives the TRIGGER_T[1](To) pin | 
-|::: |::: |[0] |IO_SELECTION[0] |RW |0x00 |Drives the TRIGGER_T[0] pin |+|::: |::: |[0] |IO_SELECTION[0] |RW |0x00 |Drives the TRIGGER_T[0](Ti) pin |
 ^0x0004 ^0x0010 ^REG_CONFIG_TRIGGER_I ^^^^Configure Digital Triggering ^ ^0x0004 ^0x0010 ^REG_CONFIG_TRIGGER_I ^^^^Configure Digital Triggering ^
 | | |[9:8] |FALL_EDGE |RW |0x00 |Enable falling edge triggering for TRIGGER[0] or TRIGGER[1] pin | | | |[9:8] |FALL_EDGE |RW |0x00 |Enable falling edge triggering for TRIGGER[0] or TRIGGER[1] pin |
Line 133: Line 151:
 | | |[31:0] |TRIGGER_DELAY |RW |0x00 |Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger. | | | |[31:0] |TRIGGER_DELAY |RW |0x00 |Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger. |
 ^0x0011 ^0x0044 ^REG_STREAMING ^^^^Controls Streaming Mode ^ ^0x0011 ^0x0044 ^REG_STREAMING ^^^^Controls Streaming Mode ^
-| | |[0] |STREAMING |RW |0x00 |If the streaming bit is set, after the trigger condition is met data will be continuosly  captured by the DMA. The streaming bit must be set to 0 to reset triggering.  | +| | |[0] |STREAMING |RW |0x00 |If the streaming bit is set, after the trigger condition is met data will be continuously captured by the DMA. The streaming bit must be set to 0 to reset triggering.  | 
-^Fri Jun  7 14:21:18 2019 ^^^^^^+^0x0012 ^0x0048 ^REG_TRIGGER_HOLDOFF ^^^^Controls hold off time ^ 
 +| | |[31:0] |TRIGGER_HOLDOFF |RW |0x00 |Defines the time interval, after a trigger event, where the next trigger events will be ignored, until the end of the interval. The time interval is set by counter. Down-counting on the ADC clock(100MHz). The value written in the register is loaded in the counter at a trigger event. | 
 +^0x0013 ^0x004c ^REG_TRIGGER_OUT_HOLD_PINS ^^^^Controls external trigger hold time ^ 
 +| | |[19:0] |TRIGGER_OUT_HOLD_PINS |RW |0x00 |Defines a time period, in which the external trigger pins, configured as outputs, will hold the new logic level after a transition. The down-counter, counting on ADC clock, is loaded with the value written in the register after a new transition of the source trigger signal, if the counter is inactive. | 
 +^Tue Sep  1 09:58:53 2020 ^^^^^^ 
 + 
 +===== Aditional notes =====
  
-==== Aditional notes ==== 
 <note important>Instrument triggering in only available from major version 3.</note> <note important>Instrument triggering in only available from major version 3.</note>
  
-==== References ====+===== References =====
   * [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_adc_trigger | AXI_ADC_TRIGGER source code]] \\   * [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_adc_trigger | AXI_ADC_TRIGGER source code]] \\
   * [[https://wiki.analog.com/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\   * [[https://wiki.analog.com/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\
resources/fpga/docs/axi_adc_trigger.txt · Last modified: 13 Oct 2021 09:56 by Iulia Moldovan

Page Tools