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Generic AXI ADC IP core

The following wiki page presents a generic framework, which is used to design and develop an AXI based IP core for interfacing an ADC device with a high speed serial (JESD204B) or source synchronous parallel interface (LVDS/CMOS). This is a generic framework, there can be minor differences on each and every IP, the user should study this wiki page along with the IP's wiki page.

The main role of this page to ease the understanding of each ADC IP, and to provide a base knowledge which can be used to develop new IPs for currently unsupported devices.

Any kind of feedback regarding the ADC IP architecture or the following document is highly appreciated and can be addressed through the FPGA Reference Designs community forum.

Architecture

The main function of an AXI ADC IP is to handle all the low level signalling, which is defined by the device's digital data interface, and to forward the received data to a more simple FIFO interface. Beside this functionality there are a few processing modules inside the data path of the core, which can be used for signal conditioning. All these processing modules are optional, the are enabled or disabled by setting the appropriate parameters. The following block diagram presents a generic AXI ADC IP cores data path.

Receiver PHY

The most important part of the core is the Receiver PHY module. This module contains all the IO primitive instantiations and all the control logic required to receive data from the device.

Currently the Receiver PHY supports several different receive interface:

All these interfaces are supported on both Altera (Intel) and Xilinx devices.

This module is perfect choice for those, who wants a HDL logic for the device interface, with a minimal resource footprint.

(1) The receive module contains just the Transport Layer of the JESD204B interface. Lower layers are implemented by other cores.

ADC channel

Data format module
DC Offset correction module
IQ correction module
PN Monitor

TODO: wiki page about each module TODO: describe the (Write) FIFO interface

ADC core

The ADC core is the top file of the IP core, the naming convention of this file is: axi_<device_name>.v . Here are instantiated all the internal module discussed above, and a wrapper module (up_axi), which converts the AXI interface into a more simplistic addressable, memory mapped interface, so called microprocessor interface or uP interface. This interface is used to interconnect the different memory mapped module pieces.

Signal and Interface Pins

A generic AXI ADC core have at least three different interfaces:

The physical data interface (LVDS or CMOS) or the JESD204B data interface from the link layer
Write FIFO interface of the receiver or sink module (e.g. DMA)
AXI Slave Memory Mapped interface for register map access

Interface	Pin	Type	Description
LVDS or CMOS RX interface
	`rx_clk_in_[p\|n]`	clock input	clock input
	`rx_data_in_[p\|n]`	input[resolution-1:0]	parallel data input
	`rx_frame_in_[p\|n]`	input	frame input signal (optional/device specific)
	`rx_or_in_[p\|n]`	input	over range input (optional/device specific)
JESD RX interface
	`rx_clk`	clock input	core clock
	`rx_sof`	input[3:0]	start of frame signal
	`rx_data`	input[DW-1:0]	data input; DW=32*MAX_LANE_NO
	`rx_ready`	output	ready, core always ready (tied to HIGH)
	`rx_valid`	input	data valid
Write FIFO interface
	`adc_clk`	clock output	Interface's clock signal
	`adc_enable_0`	output	Enable signal for the first channel, asserted if channel is active
	`adc_valid_0`	output	Data valid signal for the first channel, to validate data on the bus
	`adc_data_0`	output[DW-1:0]	Data signal for the first channel
	`adc_enable_x`	output	Enable signal for the channel x, asserted if channel is active
	`adc_valid_x`	output	Data valid signal for the channel x, to validate data on the bus
	`adc_data_x`	output[DW-1:0]	Data signal for the channel x
	`adc_dovf`	input	Data overflow signal from the receiver or sink module (e.g DMA)
	`adc_dunf`	input	Data underflow signal from the receiver or sink module (e.g DMA)
AXI Memory Map Slave
	`s_axi_*`		Standard AXI Slave Memory Map interface for register map access

Register Map

TODO: wiki page about the register map architecture

present the AXI Memory Mapped interface
talk about the UP_AXI wrapper and the simplified register interface
present read and write logic
present CDC circuits

The following block diagram presents the different register maps physical location in the core. These register maps are generic and can be found in each AXI ADC core.

The base and ADC common register map is implemented in the same verilog file. It contains registers which controls and monitors the overall core, like:

Reset bits
Attributes of the receiver interface module
DRP (Dynamic Reconfiguration Port) access for different IO resources (Clock Management Units, PLLs, Gigabit Transceivers etc.)
Status registers (PN Monitor status, frequency of the interface clock)

The ADC Common register map is implemented in the up_adc_common.v verilog file. To find the instantiation of this module search for up_adc_common inside the IP's directory.

The ADC Channel register map controls and monitors channel specific attributes. Each channel of the core has an individual channel register map. It contains all the registers, which are necessary to control and monitor the processing modules of the data path. For detailed description of the available processing modules see ADC channel section.

The ADC Channel register map is implemented in the up_adc_channel.v verilog file. To find the instantiation of this module search for up_adc_channel inside the IP's directory.

Typical Register Map base addresses

Base (common to all cores)

Click to expand regmap

0x0000	0x0000	REG_VERSION				Version and Scratch Registers
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION[31:0]	RO	0x00000000	Version number. Unique to all cores.
0x0001	0x0004	REG_ID				Version and Scratch Registers
		[31:0]	ID[31:0]	RO	0x00000000	Instance identifier number.
0x0002	0x0008	REG_SCRATCH				Version and Scratch Registers
		[31:0]	SCRATCH[31:0]	RW	0x00000000	Scratch register.
0x0003	0x000c	REG_CONFIG				Version and Scratch Registers
		[0]	IQCORRECTION_DISABLE	RO	0x0	If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
		[1]	DCFILTER_DISABLE	RO	0x0	If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
		[2]	DATAFORMAT_DISABLE	RO	0x0	If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
		[3]	USERPORTS_DISABLE	RO	0x0	If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
		[4]	MODE_1R1T	RO	0x0	If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
		[5]	DELAY_CONTROL_DISABLE	RO	0x0	If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
		[6]	DDS_DISABLE	RO	0x0	If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
		[7]	CMOS_OR_LVDS_N	RO	0x0	CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
		[8]	PPS_RECEIVER_ENABLE	RO	0x0	If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
		[9]	SCALECORRECTION_ONLY	RO	0x0	If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)
		[12]	EXT_SYNC	RO	0x0	If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
		[13]	RD_RAW_DATA	RO	0x0	If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel.
0x0004	0x0010	REG_PPS_IRQ_MASK				PPS Interrupt mask
		[0]	PPS_IRQ_MASK	RW	0x1	Mask bit for the 1PPS receiver interrupt
0x0007	0x001c	REG_FPGA_INFO				FPGA device information Intel encoded values Xilinx encoded values
		[31:24]	FPGA_TECHNOLOGY	RO	0x0	Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
		[23:16]	FPGA_FAMILY	RO	0x0	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
		[15:8]	SPEED_GRADE	RO	0x0	Encoded value describing the FPGA's speed-grade
		[7:0]	DEV_PACKAGE	RO	0x0	Encoded value describing the device package. The package might affect high-speed interfaces
Tue Mar 14 10:17:59 2023

ADC Common (axi_ad*)

Click to expand regmap

0x0010	0x0040	REG_RSTN				ADC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[2]	CE_N	RW	0x0	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
		[1]	MMCM_RSTN	RW	0x0	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL				ADC Interface Control & Status
		[16]	SDR_DDR_N	RW	0x0	Interface type (1 represents SDR, 0 represents DDR)
		[15]	SYMB_OP	RW	0x0	Select symbol data format mode (0x1)
		[14]	SYMB_8_16B	RW	0x0	Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
		[12:8]	NUM_LANES[4:0]	RW	0x0	Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.
		[3]	SYNC	RW	0x0	Initialize synchronization between multiple ADCs
		[2]	R1_MODE	RW	0x0	Select number of RF channels 1 (0x1) or 2 (0x0).
		[1]	DDR_EDGESEL	RW	0x0	Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.
		[0]	PIN_MODE	RW	0x0	Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.
0x0012	0x0048	REG_CNTRL_2				ADC Interface Control & Status
		[1]	EXT_SYNC_ARM	RW	0x0	Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[2]	EXT_SYNC_DISARM	RW	0x0	Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[8]	MANUAL_SYNC_REQUEST	RW	0x0	Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x0013	0x004c	REG_CNTRL_3				ADC Interface Control & Status
		[8]	CRC_EN	RW	0x0	Setting this bit will enable the CRC generation.
		[7:0]	CUSTOM_CONTROL	RW	0x00	ADAQ8092 Select output format decode mode. - bit [0] - enables digital output randomizer decode - bit [1] - enables alternate bit polarity decode AD4858 Select data format/oversampling - bit [2] - enable oversampling - bits [1:0] packet format selection: 0 = 20 bit 1 = 24 bit 2 = 32 bit 3 = 32 bit AD7606X_PI Select the parallel interface's operation mode - bit [2] - change mode with the selected one - bits [1:0] - requested operation mode: 0 = SIMPLE 1 = CRC_ENABLED 2 = STATUS_HEADER 3 = CRC_STATUS 07 Mar 2023 17:38 · Andrei Grozav
0x0015	0x0054	REG_CLK_FREQ				ADC Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x0000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO				ADC Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x0000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS				ADC Interface Control & Status
		[4]	ADC_CTRL_STATUS	RO	0x0	If set, indicates that the device's register data is available on the data bus.
		[3]	PN_ERR	RO	0x0	If set, indicates pn error in one or more channels.
		[2]	PN_OOS	RO	0x0	If set, indicates pn oos in one or more channels.
		[1]	OVER_RANGE	RO	0x0	If set, indicates over range in one or more channels.
		[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_DELAY_CNTRL				ADC Interface Control & Status(`Deprecated from version 9`)
		[17]	DELAY_SEL	RW	0x0	Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.
		[16]	DELAY_RWN	RW	0x0	Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.
		[15:8]	DELAY_ADDRESS[7:0]	RW	0x00	Delay address, the range depends on the interface pins, data pins are usually at the lower range.
		[4:0]	DELAY_WDATA[4:0]	RW	0x0	Delay write data, a value of 1 corresponds to (1/200)ns for most devices.
0x0019	0x0064	REG_DELAY_STATUS				ADC Interface Control & Status(`Deprecated from version 9`)
		[9]	DELAY_LOCKED	RO	0x0	Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.
		[8]	DELAY_STATUS	RO	0x0	If set, indicates busy status (access pending). The read data may not be valid if this bit is set.
		[4:0]	DELAY_RDATA[4:0]	RO	0x0	Delay read data, current delay value in the elements
0x001A	0x0068	REG_SYNC_STATUS				ADC Synchronization Status register
		[0]	ADC_SYNC	RO	0x0	ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems.
0x001C	0x0070	REG_DRP_CNTRL				ADC Interface Control & Status
		[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[27:16]	DRP_ADDRESS[11:0]	RW	0x00	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backward compatibility.
0x001D	0x0074	REG_DRP_STATUS				ADC Interface Control & Status
		[17]	DRP_LOCKED	RO	0x0	If set indicates that the DRP has been locked.
		[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x00	Reserved for backward compatibility.
0x001E	0x0078	REG_DRP_WDATA				ADC DRP Write Data
		[15:0]	DRP_WDATA[15:0]	RW	0x00	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F	0x007c	REG_DRP_RDATA				ADC DRP Read Data
		[15:0]	DRP_RDATA[15:0]	RO	0x00	DRP read data (does not include GTX lanes).
0x0020	0x0080	REG_ADC_CONFIG_WR				ADC Write Configuration Data
		[31:0]	ADC_CONFIG_WR[31:0]	RW	0x0000	Custom Write to the available registers.
0x0021	0x0084	REG_ADC_CONFIG_RD				ADC Read Configuration Data
		[31:0]	ADC_CONFIG_RD[31:0]	RO	0x0000	Custom read of the available registers.
0x0022	0x0088	REG_UI_STATUS				User Interface Status
		[2]	UI_OVF	RW1C	0x0	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[1]	UI_UNF	RW1C	0x0	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[0]	UI_RESERVED	RW1C	0x0	Reserved for backward compatibility.
0x0023	0x008c	REG_ADC_CONFIG_CTRL				ADC RD/WR configuration
		[31:0]	ADC_CONFIG_CTRL[31:0]	RW	0x0000	Control RD/WR requests to the device's register map: bit 1 - RD ('b1) , WR ('b0), bit 0 - enable WR/RD operation.
0x0028	0x00a0	REG_USR_CNTRL_1				ADC Interface Control & Status
		[7:0]	USR_CHANMAX[7:0]	RW	0x00	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0029	0x00a4	REG_ADC_START_CODE				ADC Synchronization start word
		[31:0]	ADC_START_CODE[31:0]	RW	0x00000000	This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).
0x002E	0x00b8	REG_ADC_GPIO_IN				ADC GPIO inputs
		[31:0]	ADC_GPIO_IN[31:0]	RO	0x00000000	This reads auxiliary GPI pins of the ADC core
0x002F	0x00bc	REG_ADC_GPIO_OUT				ADC GPIO outputs
		[31:0]	ADC_GPIO_OUT[31:0]	RW	0x00000000	This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
0x0030	0x00c0	REG_PPS_COUNTER				PPS Counter register
		[31:0]	PPS_COUNTER[31:0]	RO	0x00000000	Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.
0x0031	0x00c4	REG_PPS_STATUS				PPS Status register
		[0]	PPS_STATUS	RO	0x0	If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active.
Fri Aug 11 18:29:53 2023

ADC Channel (axi_ad*)

Click to expand regmap

0x0100	0x0400	REG_CHAN_CNTRL				ADC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[11]	ADC_LB_OWR	RW	0x0	If set, forces ADC_DATA_SEL to 1, enabling data loopback
		[10]	ADC_PN_SEL_OWR	RW	0x0	If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
		[9]	IQCOR_ENB	RW	0x0	if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[8]	DCFILT_ENB	RW	0x0	if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
		[6]	FORMAT_SIGNEXT	RW	0x0	if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[5]	FORMAT_TYPE	RW	0x0	Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[4]	FORMAT_ENABLE	RW	0x0	Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[3]	RESERVED	RO	0x0	Reserved for backward compatibility.
		[2]	RESERVED	RO	0x0	Reserved for backward compatibility.
		[1]	ADC_PN_TYPE_OWR	RW	0x0	If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
		[0]	ENABLE	RW	0x0	If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected.
0x0101	0x0404	REG_CHAN_STATUS				ADC Interface Control & Status
		[12]	CRC_ERR	RW1C	0x0	CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.
		[11:4]	STATUS_HEADER	RO	0x00	The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).
		[2]	PN_ERR	RW1C	0x0	PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.
		[1]	PN_OOS	RW1C	0x0	PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.
		[0]	OVER_RANGE	RW1C	0x0	If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.
0x0102	0x0408	REG_CHAN_RAW_DATA				ADC Raw Data Reading
		[31:0]	ADC_READ_DATA[31:0]	RO	0x0000	Raw data read from the ADC.
0x0104	0x0410	REG_CHAN_CNTRL_1				ADC Interface Control & Status
		[31:16]	DCFILT_OFFSET[15:0]	RW	0x0000	DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
		[15:0]	DCFILT_COEFF[15:0]	RW	0x0000	DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
0x0105	0x0414	REG_CHAN_CNTRL_2				ADC Interface Control & Status
		[31:16]	IQCOR_COEFF_1[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[15:0]	IQCOR_COEFF_2[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x0106	0x0418	REG_CHAN_CNTRL_3				ADC Interface Control & Status
		[19:16]	ADC_PN_SEL[3:0]	RW	0x0	Selects the PN monitor sequence type (available only if ADC supports it). - 0x0: pn9a (device specific, modified pn9) - 0x1: pn23a (device specific, modified pn23) - 0x4: pn7 (standard O.150) - 0x5: pn15 (standard O.150) - 0x6: pn23 (standard O.150) - 0x7: pn31 (standard O.150) - 0x9: pnX (device specific, e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
		[3:0]	ADC_DATA_SEL[3:0]	RW	0x0	Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)
0x0108	0x0420	REG_CHAN_USR_CNTRL_1				ADC Interface Control & Status
		[25]	USR_DATATYPE_BE	RO	0x0	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[24]	USR_DATATYPE_SIGNED	RO	0x0	The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[23:16]	USR_DATATYPE_SHIFT[7:0]	RO	0x00	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:8]	USR_DATATYPE_TOTAL_BITS[7:0]	RO	0x00	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[7:0]	USR_DATATYPE_BITS[7:0]	RO	0x00	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109	0x0424	REG_CHAN_USR_CNTRL_2				ADC Interface Control & Status
		[31:16]	USR_DECIMATION_M[15:0]	RW	0x0000	This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:0]	USR_DECIMATION_N[15:0]	RW	0x0000	This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0110	0x0440	REG_*				Channel 1, similar to register 0x100 to 0x10f.
0x0120	0x0480	REG_*				Channel 2, similar to register 0x100 to 0x10f.
0x01F0	0x07c0	REG_*				Channel 15, similar to register 0x100 to 0x10f.
Tue Mar 14 10:17:59 2023

IO Delay Control (axi_ad*)

Click to expand regmap

0x00	0x0000	REG_DELAY_CONTROL_0				Delay Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[4:0]	DELAY_CONTROL_IO_0	RW	0x00	Tap value for input/output delay primitive of the first interface line. If the delay controller is not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF. Otherwise will be the last set up value.
0x01	0x0004	REG_DELAY_CONTROL_1				Delay Control & Status
		[4:0]	DELAY_CONTROL_IO_1	RW	0x00	Tap value for input/output delay primitive of the second interface line. If the delay controller is not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF. Otherwise will be the last set up value.
0x02	0x0008	REG_*				Tap value for input/output delay primitive of the third interface line.
0x03	0x000c	REG_*				Tap value for input/output delay primitive of the fourth interface line.
0x0F	0x003c	REG_DELAY_CONTROL_F				Delay Control & Status
		[4:0]	DELAY_CONTROL_IO_F	RW	0x00	Tap value for input/output delay primitive of the last interface line. In general the data and frame lines are controlled with delay primitives, the number of registers of a controller is device specific.
Tue Mar 14 10:17:59 2023

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Analog Devices Wiki

Table of Contents

Generic AXI ADC IP core

Architecture

Receiver PHY

ADC channel

ADC core

Signal and Interface Pins

Register Map

Typical Register Map base addresses

Base (common to all cores)

ADC Common (axi_ad*)

ADAQ8092

AD4858

AD7606X_PI

ADC Channel (axi_ad*)

IO Delay Control (axi_ad*)

Analog Devices Wiki

Table of Contents

Generic AXI ADC IP core

Architecture

Receiver PHY

ADC channel

ADC core

Signal and Interface Pins

Register Map

Typical Register Map base addresses

Base (common to all cores)

ADC Common (axi_ad*)

ADAQ8092

AD4858

AD7606X_PI

ADC Channel (axi_ad*)

IO Delay Control (axi_ad*)

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