Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
resources:fpga:docs:axi_adc_ip [11 Oct 2021 14:40] Iulia Moldovan Edit next page to be Using and modifying the HDL design |
resources:fpga:docs:axi_adc_ip [13 Oct 2021 10:18] Iulia Moldovan Edit footer & cosmetic updates |
||
|---|---|---|---|
| Line 6: | Line 6: | ||
| <note important>Any kind of feedback regarding the ADC IP architecture or the following document is highly appreciated and can be addressed through the [[ez>community/fpga|FPGA Reference Designs]] community forum.</note> | <note important>Any kind of feedback regarding the ADC IP architecture or the following document is highly appreciated and can be addressed through the [[ez>community/fpga|FPGA Reference Designs]] community forum.</note> | ||
| + | |||
| ===== Architecture ===== | ===== Architecture ===== | ||
| Line 34: | Line 35: | ||
| * PN Monitor | * PN Monitor | ||
| - | TODO: wiki page about each module | ||
| - | TODO: describe the (Write) FIFO interface | ||
| ==== ADC core ==== | ==== ADC core ==== | ||
| Line 41: | Line 40: | ||
| Here are instantiated all the internal module discussed above, and a wrapper module (up_axi), which converts the AXI interface into a more simplistic addressable, memory mapped interface, so called [[/resources/fpga/docs/up_if|microprocessor interface]] or **uP interface**. | Here are instantiated all the internal module discussed above, and a wrapper module (up_axi), which converts the AXI interface into a more simplistic addressable, memory mapped interface, so called [[/resources/fpga/docs/up_if|microprocessor interface]] or **uP interface**. | ||
| This interface is used to interconnect the different memory mapped module pieces. | This interface is used to interconnect the different memory mapped module pieces. | ||
| + | |||
| ===== Signal and Interface Pins ===== | ===== Signal and Interface Pins ===== | ||
| Line 74: | Line 74: | ||
| |** AXI Memory Map Slave ** |||| | |** AXI Memory Map Slave ** |||| | ||
| | | ''s_axi_*'' || Standard AXI Slave Memory Map interface for register map access | | | | ''s_axi_*'' || Standard AXI Slave Memory Map interface for register map access | | ||
| - | ===== Register Map ===== | ||
| - | TODO: wiki page about the register map architecture | + | |
| - | * present the AXI Memory Mapped interface | + | ===== Register Map ===== |
| - | * talk about the UP_AXI wrapper and the simplified register interface | + | |
| - | * present read and write logic | + | |
| - | * present CDC circuits | + | |
| The following block diagram presents the different register maps physical location in the core. These register maps are generic and can be found in each AXI ADC core. | The following block diagram presents the different register maps physical location in the core. These register maps are generic and can be found in each AXI ADC core. | ||
| Line 98: | Line 94: | ||
| <note>The ADC Channel register map is implemented in the [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_adc_channel.v|up_adc_channel.v]] verilog file. To find the instantiation of this module search for ''up_adc_channel'' inside the IP's directory. | <note>The ADC Channel register map is implemented in the [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_adc_channel.v|up_adc_channel.v]] verilog file. To find the instantiation of this module search for ''up_adc_channel'' inside the IP's directory. | ||
| </note> | </note> | ||
| - | |||
| ==== Typical Register Map base addresses ==== | ==== Typical Register Map base addresses ==== | ||
| Line 107: | Line 102: | ||
| {{page>:resources:fpga:docs:hdl:regmap##IO Delay Control (axi_ad*)&nofooter&noeditbtn}} | {{page>:resources:fpga:docs:hdl:regmap##IO Delay Control (axi_ad*)&nofooter&noeditbtn}} | ||
| - | {{navigation #axi_ip|AXI IP#hdl|Main page#tips|Using and modifying the HDL design}} | + | {{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}} |
resources/fpga/docs/axi_adc_ip.txt · Last modified: 13 Oct 2021 10:18 by Iulia Moldovan