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resources:fpga:docs:axi_ad9963 [31 May 2017 10:04] – Adrian Costinaresources:fpga:docs:axi_ad9963 [13 Oct 2021 09:50] (current) – Edit footer & add reference to generic ADC/DAC Iulia Moldovan
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-===== AXI_AD9963 =====+====== AXI_AD9963 ======
  
-The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9963|axi_ad9963]] IP is implementing the interfacing with the [[adi>AD9963]] chip. It features a dual 12 bit ADC working up to 100MSPS and a dual 12 bit DAC with up to 170MSPS. It also features a DLL which can provide clock for both the ADC and the DAC path.+The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9963|axi_ad9963]] IP is implementing the interfacing with the [[adi>AD9963]] chip. It features a dual 12 bit ADC working up to 100MSPS and a dual 12 bit DAC with up to 170MSPS. It also features a DLL which can provide clock for both the ADC and the DAC path.\\ 
 +\\ 
 +More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]], and for DACs: [[:resources:fpga:docs:axi_dac_ip]].
  
-==== Features ====+ 
 +===== Features =====
    
   * AXI Lite control/status interface   * AXI Lite control/status interface
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   * Supports Xilinx devices   * Supports Xilinx devices
  
-==== Block Diagram ====+ 
 +===== Block Diagram =====
  
 {{ :resources:fpga:docs:axi_ad9963.svg | AXI_AD9963 Block diagram }} {{ :resources:fpga:docs:axi_ad9963.svg | AXI_AD9963 Block diagram }}
  
-==== Configuration Parameters ====+ 
 +===== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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 | ''ADC_SCALECORRECTION_ONLY'' | If IQ correction block is enabled and only the scale needs to be corrected, this should be set to 1  | 1 | | ''ADC_SCALECORRECTION_ONLY'' | If IQ correction block is enabled and only the scale needs to be corrected, this should be set to 1  | 1 |
  
-==== Interface ====+ 
 +===== Interface =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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 |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface | |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface |
  
-==== Detailed Description ====+ 
 +===== Detailed Description =====
  
 The TRX (ADC) interface is set at 100 MSPS, full duplex mode, double data rate (DDR), two channels. The clock comes from the AD9963 chip. The TRX (ADC) interface is set at 100 MSPS, full duplex mode, double data rate (DDR), two channels. The clock comes from the AD9963 chip.
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 The TX (DAC) interface works at 75MSPS data rate with interpolation by 2 on the AD9963 chip. The DAC path inside AD9963 chip works at 150MHz, pushing part of the spurs outside the 100MHz bandwidth. The design assumes that the 75MHz clock is not available in the FPGA. In order to reduce the number of PLL used in the FPGA, we are using AD9963 and a BUFR (divide by 2) to generate this clock. When the clock is generated by AD9963, DDR transfer is not available. The TX interface works at 150 MHz, SDR. The TX (DAC) interface works at 75MSPS data rate with interpolation by 2 on the AD9963 chip. The DAC path inside AD9963 chip works at 150MHz, pushing part of the spurs outside the 100MHz bandwidth. The design assumes that the 75MHz clock is not available in the FPGA. In order to reduce the number of PLL used in the FPGA, we are using AD9963 and a BUFR (divide by 2) to generate this clock. When the clock is generated by AD9963, DDR transfer is not available. The TX interface works at 150 MHz, SDR.
  
-==== Register Map ====+ 
 +===== Register Map ===== 
 +{{page>:resources:fpga:docs:reg_map_description&nofooter&noeditbtn}} 
 + 
 +==== Register Map base addresses for axi_ad9963 ==== 
 + 
 +|< 100% 5% 5% 5% 25% 5% 55% >| 
 +|Address ||Name |||Description | 
 +|DWORD |BYTE |::: |::: |::: |::: | 
 +^0x0000 ^0x0000 ^BASE ^^^See the [[#base_common_to_all_cores|Base (common to all cores)]] table for more detail ^ 
 +^0x0000 ^0x0000 ^ADC COMMON ^^^ See the [[#adc_common_axi_ad|ADC Common]] table for more detail ^ 
 +^0x0000 ^0x0000 ^ADC CHANNELS ^^^ See the [[#adc_channel_axi_ad|ADC Channel]] table for more detail ^ 
 +^0x1000 ^0x4000 ^DAC COMMON ^^^ See the [[#dac_common_axi_ad|DAC Common]] table for more detail ^ 
 +^0x1000 ^0x4000 ^DAC CHANNELS ^^^ See the [[#dac_channel_axi_ad|DAC Channel]] table for more detail ^
  
 {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}}
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 {{page>:resources:fpga:docs:hdl:regmap##DAC Channel (axi_ad*)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##DAC Channel (axi_ad*)&nofooter&noeditbtn}}
  
-==== Design Guidelines ====+ 
 +===== Design Guidelines =====
  
  In order to reduce the power and resource utilization, all the unused features should be disabled.  In order to reduce the power and resource utilization, all the unused features should be disabled.
  
-==== Software Guidelines ====+ 
 +===== Software Guidelines =====
  
 For RX PRBS data, when 2's complement mode is selected, each new word is the 1 bit shifted version of the previous word. For RX PRBS data, when 2's complement mode is selected, each new word is the 1 bit shifted version of the previous word.
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 The TX interface testing is done by writing 1024 samples of PRBS data and checking the BIST signature values for both the I and the Q side. Interpolation should not be active during the BIST testing. The TX interface testing is done by writing 1024 samples of PRBS data and checking the BIST signature values for both the I and the Q side. Interpolation should not be active during the BIST testing.
  
-==== References ==== 
-  * [[https://github.com/analogdevicesinc/hdl/tree/dev/library/axi_ad9963| AD9963 IP source code]] \\ 
-  * [[http://www.analog.com/en/products/rf-microwave/communications-analog-front-ends/mixed-signal-frontends/ad9963.html | AD9963 chip information ]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\ 
-  * [[https://github.com/analogdevicesinc/linux/tree/m2k | ADI Linux repository ]] 
-  * [[http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf | 7 Series IO]] \\ 
-  * [[http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf | 7 Series Clocking]] \\ 
-  * [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf | 7 Series libraries]] \\ 
  
-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Tips}}+===== References ===== 
 + 
 +  * [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9963| AD9963 IP source code]] \\ 
 +  * [[adi>en/products/rf-microwave/communications-analog-front-ends/mixed-signal-frontends/ad9963.html | AD9963 chip information ]] 
 +  * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\ 
 +  * [[https://github.com/analogdevicesinc/linux/ | ADI Linux repository ]] 
 +  * [[xilinx>support/documentation/user_guides/ug471_7Series_SelectIO.pdf | 7 Series IO]] \\ 
 +  * [[xilinx>support/documentation/user_guides/ug472_7Series_Clocking.pdf | 7 Series Clocking]] \\ 
 +  * [[xilinx>support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf | 7 Series libraries]] \\
  
 +{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_ad9963.1496217888.txt.gz · Last modified: 31 May 2017 10:04 by Adrian Costina

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