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resources:fpga:docs:axi_ad9643 [11 Oct 2021 14:41] – Edit next page to be Using and modifying the HDL design Iulia Moldovan | resources:fpga:docs:axi_ad9643 [13 Oct 2021 09:46] – Edit footer & add reference to generic ADC Iulia Moldovan | ||
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- | ===== AXI_AD9643 IP core (Obsolete)===== | + | ====== AXI_AD9643 IP core (Obsolete) |
<WRAP round important 65%> | <WRAP round important 65%> | ||
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</ | </ | ||
- | The [[https:// | + | The [[https:// |
- | An AXI Memory Map interface is used for configuration. The data is output using a FIFO interface. | + | An AXI Memory Map interface is used for configuration. The data is output using a FIFO interface.\\ |
+ | \\ | ||
+ | More about the generic framework interfacing ADCs can be read here: [[: | ||
- | ==== Features ==== | + | |
+ | ===== Features | ||
* AXI based configuration \\ | * AXI based configuration \\ | ||
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* Configurable line delays \\ | * Configurable line delays \\ | ||
* Vivado compatible \\ | * Vivado compatible \\ | ||
- | * | + | |
- | ==== Block Diagram ==== | + | |
+ | ===== Block Diagram | ||
{{ : | {{ : | ||
- | ==== Configuration | + | |
+ | ===== Configuration | ||
^ Name ^ Description ^ Default Value^ | ^ Name ^ Description ^ Default Value^ | ||
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| '' | | '' | ||
- | ==== Interface ==== | + | |
+ | ===== Interface | ||
^ Interface ^ Pin ^ Type ^ Description ^ | ^ Interface ^ Pin ^ Type ^ Description ^ | ||
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| | '' | | | '' | ||
\\ | \\ | ||
- | ==== Detailed Architecture ==== | + | |
+ | ===== Detailed Architecture | ||
{{ : | {{ : | ||
- | \\ | + | |
- | ==== Detailed Description ==== | + | |
+ | ===== Detailed Description | ||
The top module, axi_ad9643, instantiates: | The top module, axi_ad9643, instantiates: | ||
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- | ==== Register Map ==== | + | ===== Register Map ===== |
{{page>: | {{page>: | ||
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{{page>: | {{page>: | ||
- | ==== Design Guidelines ==== | + | |
+ | ===== Design Guidelines | ||
The IP was developed part of the [[/ | The IP was developed part of the [[/ | ||
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The example design uses a processor to program all the registers. If no processor is available in your system, you can create your own IP starting from the interface module. | The example design uses a processor to program all the registers. If no processor is available in your system, you can create your own IP starting from the interface module. | ||
- | ==== Software Guidelines ==== | + | |
+ | ===== Software Guidelines | ||
The software for this IP can be found as part of the FMCOMMS1 Reference Design at: [[https:// | The software for this IP can be found as part of the FMCOMMS1 Reference Design at: [[https:// | ||
Linux is supported also using [[https:// | Linux is supported also using [[https:// | ||
- | ==== References ==== | + | |
+ | ===== References | ||
* [[https:// | * [[https:// | ||
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* [[xilinx> | * [[xilinx> | ||
* [[xilinx> | * [[xilinx> | ||
- | * [[xilinx> | + | * [[xilinx> |
- | + | ||
- | {{navigation #axi_ip|AXI IP#hdl|Main page# | + | |
+ | {{navigation HDL User Guide# |