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resources:fpga:docs:axi_ad9643 [11 Oct 2021 14:41] – Edit next page to be Using and modifying the HDL design Iulia Moldovanresources:fpga:docs:axi_ad9643 [13 Oct 2021 09:46] – Edit footer & add reference to generic ADC Iulia Moldovan
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-===== AXI_AD9643 IP core (Obsolete)=====+====== AXI_AD9643 IP core (Obsolete) ======
  
 <WRAP round important 65%> <WRAP round important 65%>
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 </WRAP> </WRAP>
  
-The [[https://github.com/analogdevicesinc/hdl/tree/hdl_2016_r1/library/axi_ad9643|axi_ad9643]] IP core can be used to interface the [[adi>AD9643]] dual analog to digital converter. +The [[https://github.com/analogdevicesinc/hdl/tree/hdl_2016_r1/library/axi_ad9643|axi_ad9643]] IP core can be used to interface the [[adi>AD9643]] dual ADC. 
-An AXI Memory Map interface is used for configuration. The data is output using a FIFO interface.+An AXI Memory Map interface is used for configuration. The data is output using a FIFO interface.\\ 
 +\\ 
 +More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]].
  
-==== Features ====+ 
 +===== Features =====
  
   * AXI based configuration \\   * AXI based configuration \\
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   * Configurable line delays \\   * Configurable line delays \\
   * Vivado compatible \\   * Vivado compatible \\
-  *  + 
-==== Block Diagram ====+ 
 +===== Block Diagram =====
  
 {{  :resources:fpga:docs:adc_lvds_1.svg | AXI_AD9643 Block diagram }} {{  :resources:fpga:docs:adc_lvds_1.svg | AXI_AD9643 Block diagram }}
  
-==== Configuration Parameter ====+ 
 +===== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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 | ''IO_DELAY_GROUP'' | The delay group name which is set for the delay controller  | "adc_if_delay_group" | | ''IO_DELAY_GROUP'' | The delay group name which is set for the delay controller  | "adc_if_delay_group" |
  
-==== Interface ====+ 
 +===== Interface =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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 |              | ''up_adc_gpio_out'' | ''output[31:0]'' | GPIO OUT|  |              | ''up_adc_gpio_out'' | ''output[31:0]'' | GPIO OUT| 
 \\ \\
-==== Detailed Architecture ====+ 
 +===== Detailed Architecture =====
  
 {{  :resources:fpga:docs:axi_ad9643.svg | AXI_AD9643 IP architecture?800x600}} {{  :resources:fpga:docs:axi_ad9643.svg | AXI_AD9643 IP architecture?800x600}}
- \\ +  
-==== Detailed Description ====+ 
 +===== Detailed Description =====
  
 The top module, axi_ad9643, instantiates: \\ The top module, axi_ad9643, instantiates: \\
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-==== Register Map ====+===== Register Map ===== 
 {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}}
  
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 {{page>:resources:fpga:docs:hdl:regmap##ADC Channel (axi_ad*)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##ADC Channel (axi_ad*)&nofooter&noeditbtn}}
  
-==== Design Guidelines ====+ 
 +===== Design Guidelines =====
  
 The IP was developed part of the [[/resources//eval/user-guides/ad-fmcomms1-ebz | FMCOMMS1 Reference Design]]. The IP was developed part of the [[/resources//eval/user-guides/ad-fmcomms1-ebz | FMCOMMS1 Reference Design]].
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 The example design uses a processor to program all the registers. If no processor is available in your system, you can create your own IP starting from the interface module. The example design uses a processor to program all the registers. If no processor is available in your system, you can create your own IP starting from the interface module.
  
-==== Software Guidelines ====+ 
 +===== Software Guidelines =====
  
 The software for this IP can be found as part of the FMCOMMS1 Reference Design at: [[https://github.com/analogdevicesinc/no-OS/tree/2016_R1/fmcomms1  | No-Os Software]]. \\ The software for this IP can be found as part of the FMCOMMS1 Reference Design at: [[https://github.com/analogdevicesinc/no-OS/tree/2016_R1/fmcomms1  | No-Os Software]]. \\
 Linux is supported also using [[https://github.com/analogdevicesinc/linux | ADI Linux repository]] Linux is supported also using [[https://github.com/analogdevicesinc/linux | ADI Linux repository]]
  
-==== References ====+ 
 +===== References =====
  
   * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2016_r1/library/axi_ad9643| AD9643 IP source code]] \\   * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2016_r1/library/axi_ad9643| AD9643 IP source code]] \\
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   * [[xilinx>support/documentation/user_guides/ug471_7Series_SelectIO.pdf | 7 Series IO]] \\   * [[xilinx>support/documentation/user_guides/ug471_7Series_SelectIO.pdf | 7 Series IO]] \\
   * [[xilinx>support/documentation/user_guides/ug472_7Series_Clocking.pdf | 7 Series Clocking]] \\   * [[xilinx>support/documentation/user_guides/ug472_7Series_Clocking.pdf | 7 Series Clocking]] \\
-  * [[xilinx>support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf | 7 Series libraries]] \\ +  * [[xilinx>support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf | 7 Series libraries]] 
- +
-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Using and modifying the HDL design}} +
  
 +{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_ad9643.txt · Last modified: 25 Apr 2023 09:40 by Iulia Moldovan

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