The axi_ad9467 IP core can be used to interface the AD9467 ADC.
An AXI Memory Map interface is used for configuration. The data is output using a FIFO interface.
More about the generic framework interfacing ADCs can be read here: axi_adc_ip.
| ||Core ID should be unique for each AD9467 IP in the system||0|
| ||Used to select between Virtex 6 (1) or 7 Series (0) devices||0|
| ||The delay group name which is set for the delay controller||“adc_if_delay_group”|
| ||ADC interface signals|
| || ||LVDS input clock|
| || ||LVDS input data|
| || ||LVDS input over range|
| ||Interface used to control the delay lines|
| ||Clock used by the IDELAYCTRL. Connect to 200MHz|
| ||AXI Slave Memory Map interface|
| ||FIFO interface for connecting to the DMA|
| || ||The input clock is passed through an IBUFGDS and a BUFG primitive and adc_clk reults. This is the clock domain that most of the modules of the core run on|
| || ||Set when valid data is available on the bus|
| || ||Set when the channel is enabled, activated by software|
| || ||Data bus|
| || ||Data overflow input, from the DMA|
| || ||Data underflow input.|
The top module, axi_ad9467, instantiates:
The LVDS interface module (axi_ad9467_if.v) takes at the input the lvds signals for clock, data[7:0] and over range and outputs single ended signals.
The data signals are passed through an IDELAYE2 so that each line can be delayed independently through the delay controller register map.
The latency between input and output of the interface module is 3 clock cycles.
For more information regarding the 7 Series primitives you can take a look at UG472, UG471 and UG953.
The channel module implements:
The data analyzed by the PRBS monitor is raw data received from the interface. You can select between PN9 and PN23 sequences.
The delay controller module (up_delay_cntrl) allows the dynamic reconfiguration of the IDELAYE2 block, which allows for a calibration procedure to be run by software.
Up_adc_common implements the ADC COMMON register map, allowing for basic monitoring and control of the ADC.
The IP was developed part of the AD9467-FMC-EBZ Reference Design.
The control of the AD9467 chip is done through a SPI interface, which is needed at system level.
The ADC interface signals must be connected directly to the top file of the design, as IO primitives are part of the IP.
The example design uses a DMA to move the data from the output of the IP to memory.
If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level).
The example design uses a processor to program all the registers. If no processor is available in your system, you can create your own IP starting from the interface module.