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resources:fpga:docs:axi_ad9361 [13 Oct 2021 09:38] – Edit footer & add reference to generic ADC/DAC Iulia Moldovanresources:fpga:docs:axi_ad9361 [24 May 2022 11:20] – Added note that CMOS mode works in dual port full duplex mode Adrian Costina
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 The axi_ad9361 cores architecture contains: \\ The axi_ad9361 cores architecture contains: \\
-  * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361.v#L302|Interface]] module in either CMOS or LVDS mode for [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9361/intel|Intel]] or [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9361/xilinx|Xilinx]] devices. \\+  * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361.v#L302|Interface]] module in either CMOS Dual Port Full Duplex or LVDS mode for [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9361/intel|Intel]] or [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9361/xilinx|Xilinx]] devices. \\
   * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_rx.v|Receive]] module, which contains:   * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_rx.v|Receive]] module, which contains:
     * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_rx_channel.v|ADC channel processing]] modules, one for each channel \\     * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_rx_channel.v|ADC channel processing]] modules, one for each channel \\
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 ==== Device (AD9361) Interface Description ==== ==== Device (AD9361) Interface Description ====
  
-The IP supports both LVDS and CMOS interfaces (configurable, see parameters section). It avoids all the programmable flavors of the device interface mess. The interface is in fact quite simple, in LVDS mode samples require two active clock edges and in CMOS mode a single edge. The samples are then delineated in-order using the FRAME signal. This is applicable to both DDR and SDR modes. There is a limitation though, the IP core does NOT support swapping of the data ports in CMOS mode. This option is left as a constraint. As an example the PZSDR projects uses SWAP on some boards based on the board layout.+The IP supports both LVDS and CMOS Dual Port Full Duplex interfaces (configurable, see parameters section). It avoids all the programmable flavors of the device interface mess. The interface is in fact quite simple, in LVDS mode samples require two active clock edges and in CMOS mode a single edge. The samples are then delineated in-order using the FRAME signal. This is applicable to both DDR and SDR modes. There is a limitation though, the IP core does NOT support swapping of the data ports in CMOS mode. This option is left as a constraint. As an example the PZSDR projects uses SWAP on some boards based on the board layout.
  
 Let's consider the 2R2T configuration, each frame consists of 4 samples in each direction. In LVDS-DDR mode that is 8 clock edges (4 full clock cycles) identified by a frame pattern of 8'b11110000. The IP interface logic simply collects data on consecutive 8 edges and deframes using the FRAME signal and outputs the samples. The device does the same in the transmit direction. In CMOS mode, the same is done over 4 clock edges. Let's consider the 2R2T configuration, each frame consists of 4 samples in each direction. In LVDS-DDR mode that is 8 clock edges (4 full clock cycles) identified by a frame pattern of 8'b11110000. The IP interface logic simply collects data on consecutive 8 edges and deframes using the FRAME signal and outputs the samples. The device does the same in the transmit direction. In CMOS mode, the same is done over 4 clock edges.
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 == ENABLE == == ENABLE ==
  
-The enable signal is strictly for software use and is controlled by the corresponding register bit. The core simply reflects the programmed bit as an output port. In ADI reference projects, this bit is used to activate the channel of interest. It is then used by the PACK/UNPACK cores to route the data based on total number of channels and the selected number of channels. As an example, AXI_AD9361 supports a total of 4 channels 16bits each. This corresponds to a packed channel data width of 64bits. If software enables only two channels the packed 64bits of data is exclusively shared by the enabled 2 channels (each channel gets 32bits of data).+The enable signal is strictly for software use and is controlled by the corresponding register bit. The core simply reflects the programmed bit as an output port. In ADI reference projects, this bit is used to activate the channel of interest. It is then used by the PACK/UNPACK cores to route the data based on total number of channels and the selected number of channels. As an example, AXI_AD9361 supports a total of 4 channels 16bits each. This corresponds to a packed channel data width of 64bits. If software enables only two channels the packed 64bits of data is exclusively shared by the enabled 2 channels (each channel gets 32 bits of data).
  
 == VALID == == VALID ==
resources/fpga/docs/axi_ad9361.txt · Last modified: 18 Dec 2023 18:28 by Andrei Grozav