| ||Core ID should be unique for each AD9265 IP in the system||0|
| ||Used to select between Virtex 6 (1) or 7 Series (0) devices||0|
| ||If set, the datapath processing is not generated and output data is taken directly from the AD9265||0|
| ||The delay group name which is set for the delay controller||“adc_if_delay_group”|
| ||ADC interface signals|
| || ||LVDS input clock|
| || ||LVDS input data|
| || ||LVDS input over range|
| ||Interface used to control the delay lines|
| ||Clock used by the IDELAYCTRL. Connect to 200MHz|
| ||AXI Slave Memory Map interface|
| ||FIFO interface for connecting to the DMA|
| || ||The input clock is passed through an IBUFGDS and a BUFG primitive and adc_clk reults. This is the clock domain that most of the modules of the core run on|
| || ||Output reset, on the adc_clk domain|
| || ||Set when the channel is enabled, activated by software|
| || ||Set when valid data is available on the bus|
| || ||Data bus|
| || ||Data overflow input, from the DMA|
| || ||Data underflow input. Not used|
The top module, axi_ad9265, instantiates:
The LVDS interface module, axi_ad9265_if, has as input the lvds signals for clock, data[7:0] and over range. It uses IO block primitives inside of IP to handle the input signals. The input clock is routed to a clock distribution primitive from which it drives all the ADC related processing circuitry. The data signals are passed through an IDELAYE2 so that each line can be delayed independently through the delay controller register map. The IP outputs a data value on every clock cycle, along with the over range signal. The latency between input and output of the interface module is 3 clock cycles.
The data from the interface module is processed by the adc channel module.
The channel module implements:
The data analyzed by the PRBS monitor is raw data received from the interface, before being processed in any way. Selection between PN9 and PN23 sequences can be done by programming the REG_CHAN_CNTRL_3 register.
Up_adc_common module implements the ADC COMMON register map, allowing for basic monitoring and control of the ADC.
The delay controller module, up_delay_cntrl, allows the dynamic reconfiguration of the IDELAYE2 blocks. Changing the delay on each individual line helps compensate trace differences between the data lines on the PCB. A calibration procedure can be run on software by changing the delays and monitoring the PRBS sequence.
The IP was developed part of the AD9265 Native FMC Card Reference Design.
The control of the AD9265 chip is done through a SPI interface, which is needed at system level.
The ADC interface signals must be connected directly to the top file of the design, as IO primitives are part of the IP.
The example design uses a DMA to move the data from the output of the IP to memory.
If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level).
The example design uses a processor to program all the registers. If no processor is available in your system, you can create your own IP starting from the interface module.