Address | Bits | Name | Type | Default | Description |
DWORD | BYTE |
0x0010 | 0x0040 | REG_RSTN | DAC Interface Control & Status |
| | [2] | CE_N | RW | 0x0 | Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables |
[1] | MMCM_RSTN | RW | 0x0 | MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. |
[0] | RSTN | RW | 0x0 | Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. |
0x0011 | 0x0044 | REG_CNTRL_1 | DAC Interface Control & Status |
| | [0] | SYNC | RW | 0x0 | Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears. |
[1] | EXT_SYNC_ARM | RW | 0x0 | Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
[2] | EXT_SYNC_DISARM | RW | 0x0 | Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
[8] | MANUAL_SYNC_REQUEST | RW | 0x0 | Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. |
0x0012 | 0x0048 | REG_CNTRL_2 | DAC Interface Control & Status |
| | [16] | SDR_DDR_N | RW | 0x0 | Interface type (1 represents SDR, 0 represents DDR) |
[15] | SYMB_OP | RW | 0x0 | Select data symbol format mode (0x1) |
[14] | SYMB_8_16B | RW | 0x0 | Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) |
[12:8] | NUM_LANES[4:0] | RW | 0x0 | Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane) |
[7] | PAR_TYPE | RW | 0x0 | Select parity even (0x0) or odd (0x1). |
[6] | PAR_ENB | RW | 0x0 | Select parity (0x1) or frame (0x0) mode. |
[5] | R1_MODE | RW | 0x0 | Select number of RF channels 1 (0x1) or 2 (0x0). |
[4] | DATA_FORMAT | RW | 0x0 | Select data format 2's complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1). |
[3:0] | RESERVED[3:0] | NA | 0x00 | Reserved |
0x0013 | 0x004c | REG_RATECNTRL | DAC Interface Control & Status |
| | [7:0] | RATE[7:0] | RW | 0x00 | The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock. |
0x0014 | 0x0050 | REG_FRAME | DAC Interface Control & Status |
| | [0] | FRAME | RW | 0x0 | The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears. |
0x0015 | 0x0054 | REG_STATUS1 | DAC Interface Control & Status |
| | [31:0] | CLK_FREQ[31:0] | RO | 0x00000000 | Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock. |
0x0016 | 0x0058 | REG_STATUS2 | DAC Interface Control & Status |
| | [31:0] | CLK_RATIO[31:0] | RO | 0x00000000 | Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr). |
0x0017 | 0x005c | REG_STATUS3 | DAC Interface Control & Status |
| | [0] | STATUS | RO | 0x0 | Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores. |
0x0018 | 0x0060 | REG_DAC_CLKSEL | DAC Interface Control & Status |
| | [0] | DAC_CLKSEL | RW | 0x0 | Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL |
0x001A | 0x0068 | REG_SYNC_STATUS | DAC Synchronization Status register |
| | [0] | DAC_SYNC_STATUS | RO | 0x0 | DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set. |
0x001C | 0x0070 | REG_DRP_CNTRL | DRP Control & Status |
| | [28] | DRP_RWN | RW | 0x0 | DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
[27:16] | DRP_ADDRESS[11:0] | RW | 0x00 | DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
[15:0] | RESERVED[15:0] | RO | 0x0000 | Reserved for backwards compatibility |
0x001D | 0x0074 | REG_DRP_STATUS | DAC Interface Control & Status |
| | [17] | DRP_LOCKED | RO | 0x0 | If set indicates the MMCM/PLL is locked |
[16] | DRP_STATUS | RO | 0x0 | If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
[15:0] | RESERVED[15:0] | RO | 0x0000 | Reserved for backwards compatibility |
0x001E | 0x0078 | REG_DRP_WDATA | DAC Interface Control & Status |
| | [15:0] | DRP_WDATA[15:0] | RW | 0x0000 | DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
0x001F | 0x007c | REG_DRP_RDATA | DAC Interface Control & Status |
| | [15:0] | DRP_RDATA | RO | 0x0000 | DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). |
0x0022 | 0x0088 | REG_UI_STATUS | User Interface Status |
| | [1] | UI_OVF | RW1C | 0x0 | User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. |
[0] | UI_UNF | RW1C | 0x0 | User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. |
0x0028 | 0x00a0 | REG_USR_CNTRL_1 | DAC User Control & Status |
| | [7:0] | USR_CHANMAX[7:0] | RW | 0x00 | This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). |
0x002E | 0x00b8 | REG_DAC_GPIO_IN | DAC GPIO inputs |
| | [31:0] | DAC_GPIO_IN[31:0] | RO | 0x00000000 | This reads auxiliary GPI pins of the DAC core |
0x002F | 0x00bc | REG_DAC_GPIO_OUT | DAC GPIO outputs |
| | [31:0] | DAC_GPIO_OUT[31:0] | RW | 0x00000000 | This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1). |
Thu Feb 24 13:54:22 2022 | |