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resources:fpga:docs:axi_ad7616 [11 Oct 2021 15:09] – Add footer Iulia Moldovanresources:fpga:docs:axi_ad7616 [13 Oct 2021 09:14] – Edit footer & add reference to generic ADC Iulia Moldovan
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-===== AXI_AD7616 IP core =====+====== AXI_AD7616 IP core ======
  
-The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad7616|axi_ad7616]] IP core can be used to interface the [[adi>AD7616]] device using an FPGA. The core has a AXI Memory Map interface for configuration, supports both the serial and parallel data interface of the device, and has a simple FIFO interface for the DMAC.+The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad7616|axi_ad7616]] IP core can be used to interface the [[adi>AD7616]] device using an FPGA. The core has a AXI Memory Map interface for configuration, supports both the serial and parallel data interface of the device, and has a simple FIFO interface for the DMAC. \\ 
 +\\ 
 +More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]]. 
 + 
 + 
 +===== AXI_AD7616 with Serial Interface =====
  
-==== AXI_AD7616 with Serial Interface ==== 
 {{:resources:fpga:docs:axi_ad7616_ser_v2.svg|AXI_AD7616 with Serial Interface}} {{:resources:fpga:docs:axi_ad7616_ser_v2.svg|AXI_AD7616 with Serial Interface}}
  
-==== AXI_AD7616 with Parallel Interface ====+ 
 +===== AXI_AD7616 with Parallel Interface ===== 
 {{:resources:fpga:docs:axi_ad7616_par_v2.svg|AXI_AD7616 with Parallel Interface}} {{:resources:fpga:docs:axi_ad7616_par_v2.svg|AXI_AD7616 with Parallel Interface}}
  
-==== Configuration Parameter ====+ 
 +===== Configuration Parameter =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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-==== Signal and Interface Pins ====+===== Signal and Interface Pins =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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 | ''irq'' | IRQ signal from the SPI engine ||| | ''irq'' | IRQ signal from the SPI engine |||
  
-==== Memory Map Registers ====+ 
 +===== Memory Map Registers =====
  
 If the SPI engine is active from offset **0x0000** can be found the [[/resources/fpga/peripherals/spi_engine/axi#register_map|SPI engine memory space]]. If the SPI engine is active from offset **0x0000** can be found the [[/resources/fpga/peripherals/spi_engine/axi#register_map|SPI engine memory space]].
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-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Using and modifying the HDL design}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_ad7616.txt · Last modified: 25 Apr 2023 09:34 by Iulia Moldovan

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