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resources:fpga:docs:axi_ad7616 [13 Dec 2022 11:45] sergiu arpadiresources:fpga:docs:axi_ad7616 [25 Apr 2023 09:34] (current) – Edit according to template Iulia Moldovan
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-====== AXI_AD7616 IP core ======+====== AXI_AD7616 ====== 
 + 
 +===== Overview =====
  
 The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad7616|axi_ad7616]] IP core can be used to interface the [[adi>AD7616]] device using an FPGA. The core has a AXI Memory Map interface for configuration, supports the parallel data interface of the device, and has a simple FIFO interface for the DMAC. \\ The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad7616|axi_ad7616]] IP core can be used to interface the [[adi>AD7616]] device using an FPGA. The core has a AXI Memory Map interface for configuration, supports the parallel data interface of the device, and has a simple FIFO interface for the DMAC. \\
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-===== AXI_AD7616 with Parallel Interface =====+===== Parallel interface =====
  
 {{:resources:fpga:docs:axi_ad7616_ip.svg|AXI_AD7616 with Parallel Interface}} {{:resources:fpga:docs:axi_ad7616_ip.svg|AXI_AD7616 with Parallel Interface}}
  
  
-===== Configuration Parameter =====+===== Configuration parameter =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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-===== Signal and Interface Pins =====+===== Interface signals =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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-===== Memory Map Registers =====+===== Register map =====
  
 |< 100% 5% 5% 5% 25% 5% 55% >| |< 100% 5% 5% 5% 25% 5% 55% >|
resources/fpga/docs/axi_ad7616.txt · Last modified: 25 Apr 2023 09:34 by Iulia Moldovan