Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision Last revision Both sides next revision | ||
|
resources:fpga:docs:axi_ad7616 [14 Sep 2022 09:40] Alin-Tudor Sferle axi_ad7616: Update adc_sync port type name |
resources:fpga:docs:axi_ad7616 [13 Dec 2022 11:45] sergiu arpadi |
||
|---|---|---|---|
| Line 1: | Line 1: | ||
| ====== AXI_AD7616 IP core ====== | ====== AXI_AD7616 IP core ====== | ||
| - | The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad7616|axi_ad7616]] IP core can be used to interface the [[adi>AD7616]] device using an FPGA. The core has a AXI Memory Map interface for configuration, supports both the serial and parallel data interface of the device, and has a simple FIFO interface for the DMAC. \\ | + | The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad7616|axi_ad7616]] IP core can be used to interface the [[adi>AD7616]] device using an FPGA. The core has a AXI Memory Map interface for configuration, supports the parallel data interface of the device, and has a simple FIFO interface for the DMAC. \\ |
| \\ | \\ | ||
| More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]]. | More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]]. | ||
| - | |||
| - | |||
| - | ===== AXI_AD7616 with Serial Interface ===== | ||
| - | |||
| - | {{:resources:fpga:docs:axi_ad7616_ser_v2.svg|AXI_AD7616 with Serial Interface}} | ||
| ===== AXI_AD7616 with Parallel Interface ===== | ===== AXI_AD7616 with Parallel Interface ===== | ||
| - | {{:resources:fpga:docs:axi_ad7616_par_v2.svg|AXI_AD7616 with Parallel Interface}} | + | {{:resources:fpga:docs:axi_ad7616_ip.svg|AXI_AD7616 with Parallel Interface}} |
| Line 20: | Line 15: | ||
| ^ Name ^ Description ^ Default Value^ | ^ Name ^ Description ^ Default Value^ | ||
| | ''ID'' | Core ID, it can be used in case of multiple cores on a system | 0 | | | ''ID'' | Core ID, it can be used in case of multiple cores on a system | 0 | | ||
| - | | ''IF_TYPE'' | If **0** the **SERIAL** interface is active, otherwise the **PARALLEL** | 0 | | ||
| Line 26: | Line 20: | ||
| ^ Interface ^ Pin ^ Type ^ Description ^ | ^ Interface ^ Pin ^ Type ^ Description ^ | ||
| - | | ''rx_serial'' | **A 3-wire serial interface with two SDI line** ||| | ||
| - | | | ''rx_sclk'' |''output'' | Clock | | ||
| - | | | ''rx_cs_n'' |''output'' | Chip select | | ||
| - | | | ''rx_sdo'' |''output'' | Serial data out | | ||
| - | | | ''rx_sdi_0'' |''input'' | First serial data in | | ||
| - | | | ''rx_sdi_1'' |''input'' | Second serial data in | | ||
| | ''rx_parallel'' | **Parallel interface** ||| | | ''rx_parallel'' | **Parallel interface** ||| | ||
| | | ''rx_db_o'' |''output[15:0]'' | Parallel data out | | | | ''rx_db_o'' |''output[15:0]'' | Parallel data out | | ||
| Line 38: | Line 26: | ||
| | | ''rx_rd_n'' |''output'' | Active low parallel data read control | | | | ''rx_rd_n'' |''output'' | Active low parallel data read control | | ||
| | | ''rx_wr_n'' |''output'' | Active low parallel data write control | | | | ''rx_wr_n'' |''output'' | Active low parallel data write control | | ||
| + | | | ''rx_cs_n'' |''output'' | Active low chip select | | ||
| | ''rx_control'' | **Control interface** | | | ''rx_control'' | **Control interface** | | ||
| - | | | ''rx_cnvst'' |''output'' | Conversion start signal | | + | | | ''rx_trigger '' |''input'' | End of conversion signal | |
| - | | | ''rx_busy'' |''input'' | Conversion ready signal | | + | |
| | ''s_axi_*'' | **AXI Slave Memory Map interface** ||| | | ''s_axi_*'' | **AXI Slave Memory Map interface** ||| | ||
| | ''adc_fifo'' | **Write FIFO interface for the DMAC** ||| | | ''adc_fifo'' | **Write FIFO interface for the DMAC** ||| | ||
| Line 46: | Line 34: | ||
| | | ''adc_data'' | ''output[15:0]'' | Data bus | | | | ''adc_data'' | ''output[15:0]'' | Data bus | | ||
| | | ''adc_sync'' | ''output'' | Shows the first valid beat on a sequence | | | | ''adc_sync'' | ''output'' | Shows the first valid beat on a sequence | | ||
| - | | ''irq'' | IRQ signal from the SPI engine ||| | + | | ''irq'' | IRQ signal ||| |
| ===== Memory Map Registers ===== | ===== Memory Map Registers ===== | ||
| - | |||
| - | If the SPI engine is active from offset **0x0000** can be found the [[/resources/fpga/peripherals/spi_engine/axi#register_map|SPI engine memory space]]. | ||
| - | |||
| - | The following register space is active in both PARALLEL and SERIAL mode. | ||
| |< 100% 5% 5% 5% 25% 5% 55% >| | |< 100% 5% 5% 5% 25% 5% 55% >| | ||
| Line 64: | Line 48: | ||
| ^0x0102 ^0x0408 ^REG_SCRATCH ^^^Version and Scratch Registers ^ | ^0x0102 ^0x0408 ^REG_SCRATCH ^^^Version and Scratch Registers ^ | ||
| | | |[31:0] |SCRATCH[31:0] |RW |Scratch register. | | | | |[31:0] |SCRATCH[31:0] |RW |Scratch register. | | ||
| - | ^0x0103 ^0x040C ^REG_IF_TYPE ^^^ADC Interface Control & Status ^ | ||
| - | | | |[31:0] |IF_TYPE |RO | Actual interface type, if **0** SERIAL interface is active, PARALLEL otherwise | | ||
| ^0x0110 ^0x0440 ^REG_UP_CNTRL ^^^ADC Interface Control & Status ^ | ^0x0110 ^0x0440 ^REG_UP_CNTRL ^^^ADC Interface Control & Status ^ | ||
| | | |[0] |RESETN |RW | Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. | | | | |[0] |RESETN |RW | Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. | | ||
resources/fpga/docs/axi_ad7616.txt · Last modified: 25 Apr 2023 09:34 by Iulia Moldovan