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This version (22 Feb 2017 15:12) was approved by larsc.The Previously approved version (02 Aug 2016 13:44) is available.Diff

AXI_AD7616 IP core

The axi_ad7616 IP core can be used to interface the AD7616 device using an FPGA. The core has a AXI Memory Map interface for configuration, supports both the serial and parallel data interface of the device, and has a simple FIFO interface for the DMAC.

AXI_AD7616 with Serial Interface

AXI_AD7616 with Parallel Interface

Configuration Parameter

Name Description Default Value
ID Core ID, it can be used in case of multiple cores on a system 0
IF_TYPE If 0 the SERIAL interface is active, otherwise the PARALLEL 0

Signal and Interface Pins

Interface Pin Type Description
rx_serial A 3-wire serial interface with two SDI line
rx_sclk output Clock
rx_cs_n output Chip select
rx_sdo output Serial data out
rx_sdi_0 input First serial data in
rx_sdi_1 input Second serial data in
rx_parallel Parallel interface
rx_db_o output[15:0] Parallel data out
rx_db_i input[15:0] Parallel data in
rx_db_t output active High 3-state T pin for IOBUF
rx_rd_n output Active low parallel data read control
rx_wr_n output Active low parallel data write control
rx_control Control interface
rx_cnvst output Conversion start signal
rx_busy input Conversion ready signal
s_axi_* AXI Slave Memory Map interface
adc_fifo Write FIFO interface for the DMAC
adc_valid output Shows when a valid data is available on the bus
adc_data output[15:0] Data bus
adc_sync outpu Shows the first valid beat on a sequence
irq IRQ signal from the SPI engine

Memory Map Registers

If the SPI engine is active from offset 0x0000 can be found the SPI engine memory space.

The following register space is active in both PARALLEL and SERIAL mode.

Address Bits Name Type Description
DWORD BYTE
0x0100 0x0400 REG_VERSION Version and Scratch Registers
[31:0] VERSION[31:0] RO Version number.
0x0101 0x0404 REG_ID Version and Scratch Registers
[31:0] ID[31:0] RO Instance identifier number.
0x0102 0x0408 REG_SCRATCH Version and Scratch Registers
[31:0] SCRATCH[31:0] RW Scratch register.
0x0103 0x040C REG_IF_TYPE ADC Interface Control & Status
[31:0] IF_TYPE RO Actual interface type, if 0 SERIAL interface is active, PARALLEL otherwise
0x0110 0x0440 REG_UP_CNTRL ADC Interface Control & Status
[0] RESETN RW Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
[1] CNVST_EN RW Enable the CNVST pulse generator of core.
0x0111 0x0444 REG_UP_CONV_RATE ADC Interface Control & Status
[31:0] UP_CONV_RATE RW Rate of the conversion pulse signal, it's relative to the system clock (s_axis_clk).
0x0112 0x0448 REG_UP_BURST_LENGTH ADC Interface Control & Status
[4:0] UP_BURST_LENGTH RW Define the actual burst length. The value must be equal to burst length - 1 . This register is active just on PARALLEL mode.
0x0113 0x044C REG_UP_READ_DATA ADC Interface Control & Status
[31:0] UP_READ_DATA RO This register can be used to read the device registers on PARALLEL software mode.
0x0114 0x0450 REG_UP_WRITE_DATA ADC Interface Control & Status
[31:0] UP_WRITE_DATA WO This register can be used to write the device registers on PARALLEL software mode.
resources/fpga/docs/axi_ad7616.txt · Last modified: 22 Feb 2017 15:12 by larsc