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This version (27 Jan 2023 12:49) was approved by Alin-Tudor Sferle.The Previously approved version (16 Jan 2023 20:03) is available.Diff

AXI_AD7606x IP core

The axi_ad7606x IP core can be used to interface the AD7606B, AD7606C-16 and AD7606C-18 devices using an FPGA. The core supports the parallel data interface of the device, and has a simple FIFO interface for the DMAC.

More about the generic framework interfacing ADCs, that contains the up_adc_channel and up_adc_common modules, can be read here: axi_adc_ip.

IP Block Diagram

Configuration Parameters

Name Description Default Value
ID Core ID, it can be used in case of multiple cores on a system 0
DEV_CONFIG Defines the device which will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18 0
ADC_TO_DMA_N_BITS Defines the number of bits to be transmitted to DMA: 16 - AD7606B/C-16, 32 - AD7606C-18 16
ADC_N_BITS Defines the number of bits of each device: 16 - AD7606B/C-16, 18 - AD7606C-18 16
ADC_READ_MODE Defines the ADC Read Mode option: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - CRC_STATUS 0
EXTERNAL_CLK Defines the external clock option for the ADC clock: 0 - No, 1 - Yes 0

Signal and Interface Pins

Interface Pin Type Description
rx_* Parallel data/control interface
rx_db_o output[15:0] Parallel data out
rx_db_i input[15:0] Parallel data in
rx_db_t output Active high 3-state T pin for IOBUF
rx_rd_n output Active low parallel data read control
rx_wr_n output Active low parallel data write control
rx_cs_n output Active low chip select
external_clk input External clock if the corresponding option is enabled
rx_busy input Active low busy signal
rx_first_data input Active high status signal indicating when the first channel is available on the data bus
s_axi_* AXI Slave Memory Map interface
adc_* Write FIFO interface for the DMAC
adc_valid output Shows when a valid data is available on the bus
adc_data_x output[15:0] ADC data channels (x - channel number)
adc_enable_x output ADC enable signal for each channel
adc_clk output ADC clock
adc_dovf input ADC data overflow signaling

Register Map

The register map of the core contains instances of several generic register maps like ADC common, ADC channel or PWM Generator. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map.

Base (common to all cores)

Click to expand regmap

ADC Common (axi_ad*)

Click to expand regmap

ADC Channel (axi_ad*)

Click to expand regmap

PWM Generator (axi_pwm_gen)

Click to expand regmap

Theory of operation

The axi_ad7606x IP can be configured in various operation modes, this feature being integrated in the device register map. Thus, to be able to configure the operation mode and any other features available through the mentioned register map, adc_config_ctrl signal, that is available in the up_adc_common module, is used in this way: bit 1 - RD ('b1) | WR ('b0) and bit 0 - enable WR/RD operation.

ADC Register Mode (AD7606x familiy)

As regards the register mode, AD7606x family devices have the following workflow: DB[15] - RD ('b0) | WR ('b1), DB[14:8] - register address and DB[7:0] - register data or don't care data. Besides the data output signal, WR_N and RD_N signals are also used in order to make a write or read request to the device. The following timing diagram shows a parallel interface register read operation followed by a write operation.

In case of the AD7606C-18 chip, the x identifier, this being the number of the DB pins, will be the x identifier from the AD7606B or AD7606C-16 chips + 2 (e.g. DB0 from AD7606B or AD7606C-16 will be DB2 in AD7606C-18. The pinout of the AD7606C-18 chip can be obtained from the page 12 of the AD7606C-18 Datasheet.

The following timing diagrams illustrate available ADC read modes using the AD7606x family devices.

ADC Read Mode (AD7606B/C-16)

ADC Read Mode (AD7606C-18)

ADC Read Mode with CRC enabled (AD7606B/C-16)

ADC Read Mode with CRC enabled (AD7606C-18)

ADC Read Mode with Status enabled (AD7606B/C-16)

ADC Read Mode with Status enabled (AD7606C-18)

ADC Read Mode with Status and CRC enabled (AD7606B/C-16)

ADC Read Mode with Status and CRC enabled (AD7606C-18)

Software Support

Analog Devices recommends to use the provided software drivers.

References

resources/fpga/docs/axi_ad7606x.txt · Last modified: 27 Jan 2023 12:49 by Alin-Tudor Sferle