The axi_ad7606x IP core can be used to interface the AD7606B, AD7606C-16 and AD7606C-18 devices using an FPGA. The core supports the parallel data interface of the device, and has a simple FIFO interface for the DMAC.
More about the generic framework interfacing ADCs, that contains the up_adc_channel and up_adc_common modules, can be read here: axi_adc_ip.
| ||Core ID, it can be used in case of multiple cores on a system||0|
| ||Defines the device which will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18||0|
| ||Defines the number of bits to be transmitted to DMA: 16 - AD7606B/C-16, 32 - AD7606C-18||16|
| ||Defines the number of bits of each device: 16 - AD7606B/C-16, 18 - AD7606C-18||16|
| ||Defines the ADC Read Mode option: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - CRC_STATUS||0|
| ||Defines the external clock option for the ADC clock: 0 - No, 1 - Yes||0|
| ||Parallel data/control interface|
| ||Parallel data out|
| ||Parallel data in|
| ||Active high 3-state T pin for IOBUF|
| ||Active low parallel data read control|
| ||Active low parallel data write control|
| ||Active low chip select|
| ||External clock if the corresponding option is enabled|
| ||Active low busy signal|
| ||Active high status signal indicating when the first channel is available on the data bus|
| ||AXI Slave Memory Map interface|
| ||Write FIFO interface for the DMAC|
| || ||Shows when a valid data is available on the bus|
| || ||ADC data channels (x - channel number)|
| || ||ADC enable signal for each channel|
| || ||ADC clock|
| || ||ADC data overflow signaling|
The register map of the core contains instances of several generic register maps like ADC common, ADC channel or PWM Generator. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map.
The axi_ad7606x IP can be configured in various operation modes, this feature being integrated in the device register map. Thus, to be able to configure the operation mode and any other features available through the mentioned register map, adc_config_ctrl signal, that is available in the up_adc_common module, is used in this way: bit 1 - RD ('b1) | WR ('b0) and bit 0 - enable WR/RD operation.
As regards the register mode, AD7606x family devices have the following workflow: DB - RD ('b0) | WR ('b1), DB[14:8] - register address and DB[7:0] - register data or don't care data. Besides the data output signal, WR_N and RD_N signals are also used in order to make a write or read request to the device. The following timing diagram shows a parallel interface register read operation followed by a write operation.
The following timing diagrams illustrate available ADC read modes using the AD7606x family devices.
Analog Devices recommends to use the provided software drivers.