This version (20 Sep 2022 12:22) was approved by Paul Pop.


The axi_ad7768 IP core can be used to interface the AD7768 and AD7768-4 ADC, in 1, 2, 4 or 8 data lines active.

More about the generic framework interfacing ADCs can be read here: axi_adc_ip.


  • AXI based configuration
  • CRC validation flag
  • Configurable number of active data lines
  • Real-time data header access
  • Vivado and Quartus compatible

Block Diagram

 axi_ad7768 Block diagram

Configuration Parameters

Name Description Default Value
ID Core ID should be unique for each ad7768 IP in the system 0
NUM_CHANNELS Select number of ADC channels. 8 for AD7768 and 4 for AD7768-4 8


Interface Pin Type Description
Input data interface ADC data interface signals
clk_in input input clock
ready_in input input ready signal
data_in input[7:0] serial input data
sync_adc_miso input syncronization input signal
sync_adc_mosi output syncronization output signal
adc_dovf input Data overflow input, from the DMA
s axi AXI Slave Memory Map interface
adc fifo FIFO interface for connecting to the DMA
adc_clk output This is the clock domain that most of the modules of the core run on.
adc_reset output Output reset, on the adc_clk domain
adc_enable_* output Set when the channel is enabled, activated by software
adc_valid_* output Set when valid data is available on the bus
adc_data_* output[31:0] Parallel output data
adc_data output[31:0] Serial output data
adc_sync output Start of transfer flag for serial data
adc_crc_ch_mismatch output[7:0] Channels CRC mismatch flags register

Detailed Architecture

 axi_ad7768 IP architecture

Detailed Description

The top module, axi_ad7768, instantiates:

  • the ad7768 interface module
  • the ADC channel register map
  • the ADC common register map
  • the AXI handling interface

The ad7768 interface module has as input the serial data lines, the ready_in signal and the interface clock. Data is deserialized according to the number of active lanes. The interface module also implements a parallel CRC check algorithm.
The data from the interface module is processed by the adc channel module.
Up_adc_common module implements the ADC COMMON register map, allowing for basic monitoring and control of the ADC.
Up_adc_channel module implements the ADC CHANNEL register map, allowing for basic monitoring and control of the ADC's channel.

Register Map

Base (common to all cores)

Click to expand regmap

ADC Common (axi_ad*)

Click to expand regmap

ADC Channel (axi_ad*)

Click to expand regmap

Design Guidelines

The control of the ad7768 chip is done through a SPI interface, which is needed at system level.

The ADC interface signals must be connected directly to the top file of the design, as IO primitives are part of the IP.

The example design uses a DMA to move the data from the output of the IP to memory.

If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc interface module (at IP level).

The example design uses a processor to program all the registers. If no processor is available in your system, you can create your own IP starting from the interface module.

Software Guidelines

Linux is supported also using ADI Linux repository


resources/fpga/docs/ad7768.txt · Last modified: 16 Sep 2022 09:22 by Paul Pop