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resources:fpga:altera:ced1z:common_software_design [20 Aug 2012 16:26] – created Adrian Costinaresources:fpga:altera:ced1z:common_software_design [03 Jan 2013 20:42] (current) – external edit 127.0.0.1
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 Launch the **Nios II SBT** from the **//Start -> All Programs -> Altera -> Nios II EDS 11.0 -> Nios II 11.0 Launch the **Nios II SBT** from the **//Start -> All Programs -> Altera -> Nios II EDS 11.0 -> Nios II 11.0
 Software Build Tools for Eclipse (SBT)//**. Software Build Tools for Eclipse (SBT)//**.
-<note tip>NOTE: Windows 7 users will need to right-click and select **//Run as administrator//**. Another method is to right-click and select **//Properties//** and click on the //**Compatibility**// tab and select the **//Run This Program As An Administrator//** checkbox, which will make this a permanent change.</note>+<WRAP tip>NOTE: Windows 7 users will need to right-click and select **//Run as administrator//**. Another method is to right-click and select **//Properties//** and click on the //**Compatibility**// tab and select the **//Run This Program As An Administrator//** checkbox, which will make this a permanent change.</WRAP>
  
 === 1. Initialize Eclipse workspace === === 1. Initialize Eclipse workspace ===
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 {{:resources:fpga:altera:bemicro:eclipsebuildproj.png?400}} {{:resources:fpga:altera:bemicro:eclipsebuildproj.png?400}}
  
-<note important>In case an error appears at compile time with a description like : **//section .rodata loaded at [00400164,00400477] overlaps section .text loaded at [00400164,004054d7] //**  the enable_alt_load_copy_exceptions option must be unchecked from BSP Editor -> Main -> Settings -> Advanced-> hal.linker </note>+<WRAP important>In case an error appears at compile time with a description like : **//section .rodata loaded at [00400164,00400477] overlaps section .text loaded at [00400164,004054d7] //**  the enable_alt_load_copy_exceptions option must be unchecked from BSP Editor -> Main -> Settings -> Advanced-> hal.linker </WRAP>
  
 === 2. Verify the Board Connection === === 2. Verify the Board Connection ===
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-<note>The code size and start address might be different than the ones displayed in the above screenshot.</note>+<WRAP round help>The code size and start address might be different than the ones displayed in the above screenshot.</WRAP>
resources/fpga/altera/ced1z/common_software_design.txt · Last modified: 03 Jan 2013 20:42 by 127.0.0.1

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