Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| resources:fpga:altera:ced1z:adas3022 [14 Oct 2015 08:38] – Added warning note regarding non reversibility of programming the FPGA on the ADAS3022 evaluation board Adrian Costina | resources:fpga:altera:ced1z:adas3022 [11 Jan 2021 09:40] (current) – Fixed bad link for EVAL-ADAS3022 Ioana Chelaru | ||
|---|---|---|---|
| Line 3: | Line 3: | ||
| ====== Overview ====== | ====== Overview ====== | ||
| - | This document presents the steps to setup an environment for using the **[[adi>ADAS3022EDZ| EVAL-ADAS3022EDZ]]** evaluation board together with the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi>EVAL-ADAS3022| EVAL-ADAS3022EDZ]]** evaluation board together with the **[[adi> |
| {{ : | {{ : | ||
| Line 47: | Line 47: | ||
| | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS302xEDZ board. The ADAS3022.v file contains the main ADC driver module | | | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS302xEDZ board. The ADAS3022.v file contains the main ADC driver module | | ||
| | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script // | | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script // | ||
| - | | Hdl | Contains the source files for the ADAS3022 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. | + | | Hdl | Contains the source files for the ADAS3022 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. | |
| | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3022 SOPC component | | | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3022 SOPC component | | ||
| | Software | Contains the source files of the Nios2 SBT evaluation project | | | Software | Contains the source files of the Nios2 SBT evaluation project | | ||
| Line 163: | Line 163: | ||
| Before proceeding with this step, you should be satisfied with the evaluation results from the standard evaluation | Before proceeding with this step, you should be satisfied with the evaluation results from the standard evaluation | ||
| - | The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/ | + | The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/ |
| The Evaluation Board design presented on this page is different than the default design loaded on the ADAS3022EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat: | The Evaluation Board design presented on this page is different than the default design loaded on the ADAS3022EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat: | ||
resources/fpga/altera/ced1z/adas3022.1444804691.txt.gz · Last modified: 14 Oct 2015 08:38 by Adrian Costina