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resources:fpga:altera:ced1z:adas3022 [07 Nov 2012 10:25] – Updated archive. Updated Quick evaluation instructions to program also the Evaluation Board FPGA. Adrian Costinaresources:fpga:altera:ced1z:adas3022 [11 Jan 2021 09:40] (current) – Fixed bad link for EVAL-ADAS3022 Ioana Chelaru
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>ADAS3022EDZ| EVAL-ADAS3022EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-ADAS3022EDZ Evaluation Board with the CED1 board.+This document presents the steps to setup an environment for using the **[[adi>EVAL-ADAS3022| EVAL-ADAS3022EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-ADAS3022EDZ Evaluation Board with the CED1 board.
  
 {{ :resources:fpga:altera:ced1z:ced1z_adas3022.png?500 }} {{ :resources:fpga:altera:ced1z:ced1z_adas3022.png?500 }}
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 The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link. The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.
  
-The [[adi>ADAS3022]] is a complete 16-bit, 1MSPS analog to digital data acquisition system. The part includes an 8 channel low leakage multiplexer, high common mode rejection programmable differential gain stage (6 differential input ranges), a precision low drift 4.096V reference and buffer, and a 16-bit charge redistribution successive approximation register (SAR) architecture analog-to-digital converter (ADC). The ADAS3022 is an ideal replacement for a typical 16-bit data acquisition system requiring these common features and can resolve differential input ranges up to ±20.48Vpp when using ±15V supplies. +The [[adi>ADAS3022]] is a complete 16-bit, 1 MSPS, successive approximation–based analog-to-digital data acquisition system that is manufactured on Analog Devices, Inc., proprietary iCMOS® high voltage industrial process technology. The device integrates an 8-channel, low leakage multiplexer; a high-impedance programmable gain instrumentation amplifier (PGIA) stage with a high common-mode rejection; a precision, low drift 4.096 V reference and buffer; and a 16-bit charge-redistribution analog-to-digital converter (ADC) with successive approximation register (SAR) architecture. The ADAS3022 can resolve eight single-ended inputs or four fully differential inputs up to ±24.576 V when using ±15 V supplies. In addition, the device can accept the commonly used bipolar differential, bipolar single-ended, pseudo bipolar, or pseudo unipolar input signals, as shown in Table 1, thus enabling the use of almost any direct sensor interface. The ADAS3022 simplifies design challenges by eliminating signal buffering, level shifting, amplification/attenuation, common-mode rejection, settling time, or any of the other analog signal conditioning challenges while allowing smaller form factor, faster time to market, and lower costs.
-The ADAS3022 is a SAR based data acquisition system including true high impedance differential input buffers that alleviate the need for additional buffering usually required in capacitive DAC based SAR ADCs. In addition, the ADAS3022 incorporates high common mode rejection that eliminates the need for external instrumentation amplifiers typically required in applications where common mode signals are present. +
- +
-The **EVAL-ADAS302xEDZ** is an evaluation board for the ADAS302x 16-bit data acquisition system (DAS). These devices are the first integrated solution offering the usual DAS components including an 8 channel multiplexer, high impedance differential amplifier with programmable gain, a precision 16-bit successive approximation (no latency) analog to digital converter and precision 4.096V reference. The ADAS3022 and ADAS3023 are both 8 channel devices with an aggregate throughput of 1million samples per second (1MSPS).+
  
 +The **EVAL-ADAS3022EDZ** is an evaluation board for the ADAS3022 16-bit data acquisition system (DAS) with an aggregate throughput of 1 million samples per second (1MSPS).
 ===== More information ===== ===== More information =====
  
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 | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS302xEDZ board. The ADAS3022.v file contains the main ADC driver module | | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS302xEDZ board. The ADAS3022.v file contains the main ADC driver module |
 | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in ///hdl/src/HAL// and the ADAS3022 registers in ///hdl/src/inc//  | | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in ///hdl/src/HAL// and the ADAS3022 registers in ///hdl/src/inc//  |
-| Hdl | Contains the source files for the ADAS3022 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files.  \\ - The //tb// folder contains the sources of the core's testbench |+| Hdl | Contains the source files for the ADAS3022 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. |
 | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3022 SOPC component | | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3022 SOPC component |
 | Software | Contains the source files of the Nios2 SBT evaluation project | | Software | Contains the source files of the Nios2 SBT evaluation project |
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 | AVALON_MASTER_WRITEDATA_O | OUT | 32 | Master write data bus | | AVALON_MASTER_WRITEDATA_O | OUT | 32 | Master write data bus |
 | //**External connectors**// |||| | //**External connectors**// ||||
-| BDB_IO                 | I/O | 16 | Bidirectional data bus used to write/read data to/from the AD7625_26EDZ board |+| BDB_IO                 | I/O | 16 | Bidirectional data bus used to write/read data to/from the ADAS3022EDZ board |
 | BBUSY_I                | IN  | 1  | Signal that indicates the status of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes high | | BBUSY_I                | IN  | 1  | Signal that indicates the status of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes high |
-| BRD_N_O                | OUT | 1  | Signal used by the CED1Z board to read data from the AD7625_26EDZ board | +| BRD_N_O                | OUT | 1  | Signal used by the CED1Z board to read data from the ADAS3022EDZ board | 
-| BWR_N_O                | OUT | 1  | Signal used by the CED1Z board to write data to the AD7625_26EDZ board | +| BWR_N_O                | OUT | 1  | Signal used by the CED1Z board to write data to the ADAS3022EDZ board | 
-| BADDR_O                | OUT | 3  | Used to select the register to be read from the AD7625_26EDZ board. |+| BADDR_O                | OUT | 3  | Used to select the register to be read from the ADAS3022EDZ board. |
 | BRESET_O               | OUT | 1  | Used to reset the evaluation board | | BRESET_O               | OUT | 1  | Used to reset the evaluation board |
 |  **Table 2 Port description**  |||| |  **Table 2 Port description**  ||||
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 ====== Quick Evaluation ====== ====== Quick Evaluation ======
-The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder.+<note warning> After reprogramming the FPGA on the evaluation board for using the reference design you won't be able to revert to the standard evaluation programming file and you can only use the evaluation board for prototyping.  
 + 
 +Before proceeding with this step, you should be satisfied with the evaluation results from the standard evaluation  software. </note> 
 +The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder .
  
 The Evaluation Board design presented on this page is different than the default design loaded on the ADAS3022EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat: The Evaluation Board design presented on this page is different than the default design loaded on the ADAS3022EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat:
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   * 6. After the programming ends, power off the CED1Z and reprogramm it using program_fpga.bat as described above.   * 6. After the programming ends, power off the CED1Z and reprogramm it using program_fpga.bat as described above.
  
-<note> This is a one time operation, as the programming is done on a non volatile memory on the Evaluation Board. </note>+<WRAP round help> This is a one time operation, as the programming is done on a non volatile memory on the Evaluation Board. </WRAP>
  
 In order to acquire data, follow the instructions in the //**Evaluation Project Data Acquisition**// section. In order to acquire data, follow the instructions in the //**Evaluation Project Data Acquisition**// section.
  
 ====== NIOS II Software Design ====== ====== NIOS II Software Design ======
-{{page>:resources:fpga:altera:ced1z:common_nios2_software_design}}+{{page>:resources:fpga:altera:ced1z:common_software_design}}
  
 ====== Evaluation Project Data Acquisition ====== ====== Evaluation Project Data Acquisition ======
  
-After the FPGA is correctly programmed the data acquisition process can start by executing one of the three available batch scripts: +After the FPGA is correctly programmed the data acquisition process can start by executing the data_acquisition.bat script. The data acquisition is done at 1MSPS if the ADAS3022 is in warp mode or at 0.909MSPS if in normal mode. 
-  *  1. data_capture_noseq.bat, captures data from a single channel at 500 KSPS. By editting the data_capture_noseq.tcl, the channel that is to be acquired can be changed. The resulting data is stored in Acquisition.csv. +
-  *  2. data_capture4diff.bat, captures data from up to 4 differential channels. By editting the data_capture4diff.tcl, the number of channels that are to be acquired can be changed. The resulting data is stored in Acquisition.csv. The sample rate is 500 KSPS divided by the number of acquired channels. +
-  *  3. data_capture8chan.bat, captures data from up to 8 channels, referenced to GND. By editting the data_capture8chan.tcl, the number of channels that are to be acquired can be changed.  The resulting data is stored in Acquisition.csv. The sample rate is 500 KSPS divided by the number of acquired channels.+
  
-<note>When changing between the data capture scripts the system must be reinitialized by reprogramming the FPGA.</note>+The ADAS3022 can be configured by editing the data_capture.tcl script, and configuring each bit of the CONFIGURATION register.
  
-If the resulting csv file is opened with Microsoft Excel, the data will be displayed on a single column for the first script or on 8 columns for the second and third scripts. Each column represents a channel. If the ADAS3022 is configured to acquire less than 8 channels the remaining channels will have a constant value. For example, in the below picture, the ADAS3022 was configure to acquire data on 4 differential channels, a sine signal was applied on the first channel and the rest were left floating. In this case, the first column can be plotted as a sine wave, the next 3 have some noise on them, and the last 4 have a constant value of 0.+If the resulting csv file is opened with Microsoft Excel, the data will be displayed on a single column if the sequencer is disabled or on 8 columns if the basic sequencer is enabled. Each column represents a channel. If the ADAS3022 is configured to acquire less than 8 channels the remaining channels will have a constant value. For example, in the below picture, the ADAS3022 was configure to acquire data on 4 differential channels, a sine signal was applied on the first channel and the rest were left floating. In this case, the first column can be plotted as a sine wave, the next 3 have some noise on them, and the last 4 have a constant value of 0.
  
 {{ :resources:fpga:altera:ced1z:4chan.png?800 | Plot of acquired data}} {{ :resources:fpga:altera:ced1z:4chan.png?800 | Plot of acquired data}}
resources/fpga/altera/ced1z/adas3022.1352280349.txt.gz · Last modified: 07 Nov 2012 10:25 by Adrian Costina

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