This version (26 Jan 2021 01:30) was approved by Robin Getz.The Previously approved version (03 Jan 2013 20:42) is available.Diff

CED1Z FPGA Project for AD7689 with Nios driver

Supported Devices

Evaluation Boards


This document presents the steps to setup an environment for using the EVAL-AD7689EDZ evaluation board together with the EVAL-CED Converter Evaluation and Development (CED) Board, the Nios II Embedded Development Suite (EDS) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-AD7689 Evaluation Board with the CED1 board.

The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.

The AD7689 is a 8-channel, 16-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply. The AD7689 contains all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; an 8-channel, low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.

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Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Hardware Items

Below is presented the list of required hardware items:

Software Tools

Below is presented the list of required software tools:

The Quartus II design software and the Nios II EDS is available via the Altera Complete Design Suite DVD or by downloading from the web.


Extract the Lab Files

Create a folder called “ADIEvalBoard” on your PC and extract the archive to this folder. Make sure that there are NO SPACES in the directory path. After extracting the archive the following folders should be present in the ADIEvalBoard folder: EvalBoardFPGA, FPGA, Hdl, NiosCpu, Software and DataCapture .

Folder Description
EvalBoardFPGA Contains the reference project which is loaded on the EVAL-AD689EDZ board. The AD7689.v file contains the main ADC driver modules
FPGA Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script program_fpga.bat the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder.
The ip subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in /hdl/src/HAL and the AD7689 registers in /hdl/src/inc
Hdl Contains the source files for the AD7689 HDL driver:
- The doc subfolder contains a brief documentation for the core.
- The src subfolder contains the HDL source files.
- The tb folder contains the sources of the core's testbench
NiosCpu Contains the CED1Z Quartus evaluation project source files . The ip subfolder contains the AD7689 QSYS component
Software Contains the source files of the Nios2 SBT evaluation project
DataCapture Contains the script files used for data acquisition

Install the USB-Blaster Device Driver

The USB Blaster is used to program the FPGA on the CED1Z board and also for data exchange between the system and a PC. To install the driver plug the Terasic USB Blaster into one of the PCs USB ports. Your Windows PC will find the new hardware and try to install the driver.

Since Windows cannot locate the driver for the device the automatic installation will fail and the driver has to be installed manually. In the Device Manager right click on the USB-Blaster device and select Update Driver Software.

In the next dialog box select the option Browse my computer for driver software. A new dialog will open where it is possible to point to the driver’s location. Set the location to altera\11.0\quartus\drivers\usb-blaster and press Next.

If Windows presents you with a message that the drivers have not passed Windows Logo testing, please click “Install this driver software anyway”. Upon installation completion a message will be displayed to inform that the installation is finished.


30 Nov 2011 11:18 · Adrian Costina

AD7689 Evaluation Project Overview

The evaluation project contains all the source files needed to build a system that can be used to configure the AD7689 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the SRAM of the CED1Z board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis.


The following components are implemented in the FPGA design:

Name Address IRQ
CPU 0x00000800 -
PLL 0x00000000 -
ONCHIP_MEM 0x00002000 -
LEDS 0x00000010 -
SYSID 0x00000020 -
SRAM 0x00400000 -
UCPROBE_UART 0x00000028 0
JTAG_UART_0 0x00000030 1
SYS_TIMER 0x00000040 2
PWR_DATA 0x00000060 -
I2C_INT 0x00000080 -
PWR_EN_CLK 0x000000a0 -
AD7689_0 0x000000c0 -
Table 1 System components

The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the SRAM, a module which implements an Avalon master interface which is used to write data directly in the SRAM and a module which communicates with the evaluation board. Following is presented a block diagram of the HDL core and a description of the interface signals.

Avalon core pinout diagram

Table 2 describes the port definitions of the Avalon peripheral:

Port Direction Width Description
Generic pins
FPGA_CLK_I IN 1 System clock. Designed with a 98MHz clock
RESET_I IN 1 System reset
Avalon Slave Interface
AVALON_WRITEDATA_I IN 32 Slave write data bus
AVALON_WRITE_I IN 1 Slave write data request
AVALON_READ_I IN 1 Slave read data request
AVALON_ADDRESS_I IN 2 Slave address bus
AVALON_READDATA_O OUT 32 Slave read data bus
Avalon Master Interface
AVALON_MASTER_WAITREQUEST IN 1 Master wait request signal
AVALON_MASTER_ADDRESS_O OUT 32 Master address bus
AVALON_MASTER_WRITE_O OUT 1 Master write signal
AVALON_MASTER_BYTEENABLE_O OUT 4 Master byte enable signals
AVALON_MASTER_WRITEDATA_O OUT 32 Master write data bus
External connectors
BDB_IO IO 16 Bidirectional data bus used to write/read data to/from the AD7689EDZ board
BBUSY_I IN 1 Signal that indicates the status of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes high
BRD_N_O OUT 1 Signal used by the CED1Z board to read data from the AD7689EDZ board
BWR_N_O OUT 1 Signal used by the CED1Z board to write data to the AD7689EDZ board
BADDR_O OUT 5 Used to select the register to be read from the AD7689EDZ board.
BRESET_O OUT 1 Used to reset the evaluation board
Table 2 Port description

Table 3 describes the registers of the Avalon peripheral:

Name Offset Width Access Description
CONTROL_REGISTER 0 32 RW Bit 0 is used to start data acquisition
Bit 1 is used to initiate software reset of the core
Bit 2 is used to configure the Avalon write master core to write data to the same location
Bit 3 is used to write data to the AD7689 evaluation board
ACQ_COUNT_REGISTER 1 32 RW Register used to configure the number of samples to be acquired when acquisition is started
BASE_REGISTER 2 32 RW Register used to configure the base address of the memory location where the acquired data is to be written
STATUS 3 32 R Bit 0 is used to signal that the acquisition is complete
Bit 1 is used to signal that the internal memory buffer has been overflown
Bit 2 is used to signal that the user has performed a write of a read only register register
DUT_WRITE_REGISTER 4 32 W Register used to perform writes on the device under test. Bits [15:0] are used for data and [20:16] are used as address. The rest are discarded
Table 3 Register description

The follwing figure presents the timing diagram for the read operations from the AD7689 driver .

Read operations time diagram

AD7689 Evaluation Board Design

In order to acquire data from the AD7689, several modules are implemented in the evaluation board FPGA.

 Evaluation board design overview

AD7689 module

This module is the actual driver of the AD7689 data acquisition system.

 AD7689 driver pinout

Port Direction Width Description
General Connectors
FPGA_CLK_I IN 1 20 MHz clock
ADC_CLK_I IN 1 20 MHz clock
RESET_I IN 1 Module reset
CED1Z_interface connectors
WR_DATA_N_I IN 1 Signal used to write data in the driver’s internal registers, data which will be sent to the AD7689
DATA_I IN 16 Data bus, used to send new configuration words to the AD7689
DATA_CHANNELS_O OUT 128 Parallel bus to transfer the data to the CED1Z_interface module
DATA_RD_READY_O OUT 1 Signals that at port DATA_CHANNELS_O there is new data available
DATA_WR_READY_O OUT 1 Signals that the write from CED1Z_interface has been performed
AD7689 connectors
MISO_I IN 1 Signal connected to the SDO pin of the AD7689
MOSI_O OUT 1 Signal connected to the DIN pin of the AD7689
SCLK_O OUT 1 Signal connected to the SCK pin of the AD7689. 20 MHz clock
CNV_O OUT 1 Signal connected to the CNV pin of the AD7689
Table 4 Port description for the AD7689 module


This module is used to communicate with the CED1Z board. It reads the data from the AD7689 module and forwards it to the CED1Z board. It also forwards write requests from the CED1Z board to the AD7689 module, in order to reconfigure the AD7689 acquisition system. In case the acquisition is done on 8 channels, data is mapped at addresses starting from 0x10 (channel 0) to 0x17 (channel 8). In case a single channel is acquired, data is mapped sequentially on each of the eight addresses. In this case, data must be concatenated by the module running on the CED1Z board.


This module is used to generate a 20 MHz clock signal from the 100MHz external clock signal that is available on the evaluation board.

Quick Evaluation

The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder.

The Evaluation Board design presented on this page is different than the default design loaded on the AD7689EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat:

  • 1. Connect the USB-Blaster to the P2 port
  • 2. Start Quartus II, Start Tools →Programmer
  • 3. Select Mode Active Serial Programming
  • 4. Press Add File and select EvalBoardAD7689.pof
  • 5. Check Program/Configure and Press Start.
  • 6. After the programming ends, power off the CED1Z and reprogramm it using program_fpga.bat as described above.

This is a one time operation, as the programming is done on a non volatile memory on the Evaluation Board. In order to restore the original firmware on the Evaluation Board, at step 4 use the configuration file from the CD at Evaluation Board FPGA code/uMUX FPGA CED 2-2/toplevel.pof.

In order to acquire data, follow the instructions in the Evaluation Project Data Acquisition section.

NIOS II Software Design

This section presents the steps for developing a software application that will run on the CED1Z system and will be used for controlling and monitoring the operation of the ADI evaluation board.

Create a new project using the NIOS II Software Build Tools for Eclipse

Launch the Nios II SBT from the Start → All Programs → Altera → Nios II EDS 11.0 → Nios II 11.0 Software Build Tools for Eclipse (SBT).

NOTE: Windows 7 users will need to right-click and select Run as administrator. Another method is to right-click and select Properties and click on the Compatibility tab and select the Run This Program As An Administrator checkbox, which will make this a permanent change.

1. Initialize Eclipse workspace

  • When Eclipse first launches, a dialog box appears asking what directory it should use for its workspace. It is useful to have a separate Eclipse workspace associated with each hardware project that is created in SOPC Builder. Browse to the ADIEvalBoard directory and click Make New Folder to create a folder for the software project. Name the new folder “eclipse_workspace”. After selecting the workspace directory, click OK and Eclipse will launch and the workbench will appear in the Nios II perspective.

2. Create a new software project in the SBT

  • Select File → New → Nios II Application and BSP from Template.

  • Click the Browse button in the SOPC Information File Name dialog box.
  • Select the uC.sopcinfo file located in the ADIEvalBoard/FPGA directory.
  • Set the name of the Application project to “ADIEvalBoard”.
  • Select the Blank Project template under Project template.
  • Click the Finish button.

The tool will create two new software project directories. Each Nios II application has 2 project directories in the Eclipse workspace.

  • The application software project itself - this where the application lives.
  • The second is the Board Support Package (BSP) project associated with the main application software project. This project will build the system library drivers for the specific SOPC system. This project inherits the name from the main software project and appends “_bsp” to that.

Since you chose the blank project template, there are no source files in the application project directory at this time. The BSP contains a directory of software drivers as well as a system.h header file, system initialization source code and other software infrastructure.

Configure the Board Support Package

  • Configure the board support package to specify the properties of this software system by using the BSP Editor tool. These properties include what interface should be used for stdio and stderr messages, the memory in which stack and heap should be allocated and whether an operating system or network stack should be included with this BSP.
  • Right click on the ADIEvalBoard_bsp project and select Nios II → BSP Editor… from the right-click menu.

The software project provided in this lab does not make use of an operating system. All stdout, stdin and stderr messages will be directed to the jtag_uart.

  • Select the Common settings view. In the Common settings view, change the following settings:
    • Select the jtag_uart_0 for stdin, stdout and stderr messages. Note that you have more than one choice.
    • Select none for the sys_clk_timer and timestamp_timer.

The memory used by the design is should be changed from OnChip ram to SRAM for the .text region.

  • Select Linker Script tab.
  • Change .text region Linker Region Name from onchip_mem to sram.

  • Select File → Save to save the board support package configuration to the settings.bsp file.
  • Click the Generate button to update the BSP.
  • When the generate has completed, select File → Exit to close the BSP Editor.

Configure BSP Project Build Properties

In addition to the board support package settings configured using the BSP Editor, there are other compilation settings managed by the Eclipse environment such as compiler flags and optimization level.

  • Right click on the ADIEvalBoard_bsp software project and select Properties from the right-click menu.
  • On the left-hand menu, select Nios II BSP Properties.
  • During compilation, the code may have various levels of optimization which is a tradeoff between code size and performance. Change the Optimization level setting to Level 2
  • Since our software does not make use of C++, uncheck Support C++.
  • Check the Reduced device drivers option
  • Check the Small C library option
  • Press Apply and OK to regenerate the BSP and close the Properties window.

Add source code to the project

In Windows Explorer locate the project directory which contains a directory called Software. In Windows Explorer select all the files and directories from the Software folder and drag and drop them into the Eclipse software project ADIEvalBoard.

  • Select all the files and folders and drag them over the ADIEvalBoard project in the SBT window and drop the files onto the project folder.

  • A dialog box will appear to select the desired operation. Select the option Copy files and folders and press OK.

  • This should cause the source files to be physically copied into the file system location of the software project directory and register these source files within the Eclipse workspace so that they appear in the Project Explorer file listing.

Configure Application Project Build Properties

Just as you configured the optimization level for the BSP project, you should set the optimization level for the application software project ADIEvalBoard as well.

  • Right click on the ADIEvalBoard software project and select Properties from the right-click menu.
  • On the left-hand menu, select the Nios II Application Properties tab
  • Change the Optimization level setting to Level 2.
  • Press Apply and OK to save the changes.

Define Application Include Directories

Application code can be conveniently organized in a directory structure. This section shows how to define these paths in the makefile.

  • In the Eclipse environment double click on to open the file.
  • Click the Ctrl and A keys to select all the text. Click the Ctrl and C keys to copy all the text.

  • Double click on Makefile to open the file.
  • If you see the message shown here about resources being out of sync, right click on the Makefile and select Refresh.

  • Select the line APP_INCLUDE_DIRS :=

  • Click the Ctrl and V keys to replace the selected line with the include paths.

  • Click the Ctrl and S keys to save the Makefile.

Compile, Download and Run the Software Project

1. Build the Application and BSP Projects

  • Right click the ADIEvalBoard_bsp software project and choose Build Project to build the board support package.
  • When that build completes, right click the ADIEvalBoard application software project and choose Build Project to build the Nios II application.

These 2 steps will compile and build the associated board support package, then the actual application software project itself. The result of the compilation process will be an Executable and Linked Format (.elf) file for the application, the ADIEvalBoard.elf file.

In case an error appears at compile time with a description like : section .rodata loaded at [00400164,00400477] overlaps section .text loaded at [00400164,004054d7] the enable_alt_load_copy_exceptions option must be unchecked from BSP Editor → Main → Settings → Advanced→ hal.linker

2. Verify the Board Connection

The CED1Z hardware is designed with a System ID peripheral. This peripheral is assigned a unique value based on when the hardware design was last modified in the SOPC Builder tool. SOPC Builder also places this information in the .sopcinfo hardware description file. The BSP is built based on the information in the .sopcinfo file.

  • Select the ADIEvalBoard application software project.
  • Select Run → Run Configurations…
  • Select the Nios II Hardware configuration type.
  • Press the New button to create a new configuration.
  • Change the configuration name to CED1Z and click Apply.
  • On the Target Connection tab, press the Refresh Connections button. You may need to expand the window or scroll to the right to see this button.
  • Select the jtag_uart_0 as the Byte Stream Device for stdio.
  • Check the Ignore mismatched system ID option.
  • Check the Ignore mismatched system timestamp option.

3. Run the Software Project on the Target

To run the software project on the Nios II processor:

  • Before running the the software project, the FPGA located on the CED1Z must be programmed with the Nios II system image. To program the FPGA run the ADIEvalBoard/FPGA/program_fpga.bat script.
  • Press the Run button in the Run Configurations window. This will re-build the software project to create an up–to-date executable and then download the code into memory on the CED1Z hardware. The debugger resets the Nios II processor, and it executes the downloaded code. Note that the code is verified in memory before it is executed

The code size and start address might be different than the ones displayed in the above screenshot.

20 Aug 2012 16:26 · Adrian Costina

Evaluation Project Data Acquisition

After the FPGA is correctly programmed the data acquisition process can start by executing one of the three available batch scripts:

  • 1. data_capture_noseq.bat, captures data from a single channel at 250 KSPS. By editting the data_capture_noseq.tcl, the channel that is to be acquired can be changed. The resulting data is stored in Acquisition.csv.
  • 2. data_capture4diff.bat, captures data from up to 4 differential channels. By editting the data_capture4diff.tcl, the number of channels that are to be acquired can be changed. The resulting data is stored in Acquisition.csv. The sample rate is 250 KSPS divided by the number of acquired channels.
  • 3. data_capture8chan.bat, captures data from up to 8 channels, referenced to GND. By editting the data_capture8chan.tcl, the number of channels that are to be acquired can be changed. The resulting data is stored in Acquisition.csv. The sample rate is 250 KSPS divided by the number of acquired channels.

When changing between the data capture scripts the system must be reinitialized by reprogramming the FPGA.

If the resulting csv file is opened with Microsoft Excel, the data will be displayed on a single column for the first script or on 8 columns for the second and third scripts. Each column represents a channel. If the AD7689 is configured to acquire less than 8 channels the remaining channels will have a constant value. For example, in the below picture, the AD7689 was configure to acquire data on 4 differential channels, a sine signal was applied on the first channel and the rest were left floating. In this case, the first column can be plotted as a sine wave, the next 3 have some noise on them, and the last 4 have a constant value of 0.

 Plot of acquired data

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resources/fpga/altera/ced1z/ad7689.txt · Last modified: 26 Jan 2021 01:23 by Robin Getz