This document presents the steps to setup an environment for using the EVAL-AD7671CBZ evaluation board together with the EVAL-CED Converter Evaluation and Development (CED) Board and Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7671 Evaluation Board with the CED1 board.
The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.
The AD7671 is a 16-bit, 1 MSPS, charge redistribution SAR,analog-to-digital converter that operates from a single 5 V power supply. It contains a high speed 16-bit sampling ADC, a resistor input scaler that allows various input ranges, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. The AD7671 is hardware factory-calibrated and is comprehensively tested to ensure such AC parameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional DC parameters of gain, offset, and linearity. It features a very high sampling rate mode (Warp), a fast mode (Normal) for asynchronous conversion rate applications, and, for low power applications, a reduced power mode (Impulse) where the power is scaled with the throughput. It is fabricated using Analog Devices’ high performance, 0.6 micron CMOS process and is available in a 48-lead LQFP and a tiny 48-lead LFCSP, with operation specified from –40C to +85C.
The EVAL-AD7671CBZ is a fully featured evaluation kit for the AD7671. This board operates in stand alone mode or in conjunction with the Converter Evaluation and Development board, EVAL-CED1Z . When operated with the Converter Evaluation and Development board, software is provided enabling the user to perform detailed analysis of the ADC's performance.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Below is presented the list of required hardware items:
Below is presented the list of required software tools:
The Quartus II design software and the Nios II EDS is available via the Altera Complete Design Suite DVD or by downloading from the web.
Create a folder called “ADIEvalBoard” on your PC and extract the ad7671_evalboard.zip archive to this folder. Make sure that there are NO SPACES in the directory path. After extracting the archive the following folders should be present in the ADIEvalBoard folder: FPGA, Hdl, NiosCpu, Software, DataCapture
|FPGA|| Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script program_fpga.bat the FPGA with be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder.
The ip subfolder contains the HDL drivers in /hdl/src , the software drivers for HAL in /hdl/src/HAL and the AD7671 registers in /hdl/src/inc .
|Hdl|| Contains the source files for the AD7671 HDL driver:
- The doc subfolder contains a brief documentation for the driver.
- The src subfolder contains the HDL source files.
- The tb folder contains the sources of the driver's testbench.
|NiosCpu||Contains the CED1Z Quartus evaluation project source files . The ip subfolder contains the AD7671 SOPC component.|
|Software||Contains the source files of the Nios2 SBT evaluation project.|
|DataCapture||Contains the script files used for data acquisition|
The USB Blaster is used to program the FPGA on the CED1Z board and also for data exchange between the system and a PC. To install the driver plug the Terasic USB Blaster into one of the PCs USB ports. Your Windows PC will find the new hardware and try to install the driver.
Since Windows cannot locate the driver for the device the automatic installation will fail and the driver has to be installed manually. In the Device Manager right click on the USB-Blaster device and select Update Driver Software.
In the next dialog box select the option Browse my computer for driver software. A new dialog will open where it is possible to point to the driver’s location. Set the location to altera\11.0\quartus\drivers\usb-blaster and press Next.
If Windows presents you with a message that the drivers have not passed Windows Logo testing, please click “Install this driver software anyway”. Upon installation completion a message will be displayed to inform that the installation is finished.
The evaluation project contains all the source files needed to build a system that can be used to configure the AD7671 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the SRAM of the CED1Z board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis.
The following components are implemented in the FPGA design:
|Table 1 System components|
The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the SRAM, a module which implements an Avalon master interface which is used to write data directly in the SRAM and a module which is the actual driver of the DUT. The driver can also be used as standalone in FPGA designs which do not contain a softcore. Following is presented a block diagram of the HDL driver and a description of the driver's interface signals.
Table 2 describes the port definitions of the Avalon peripheral:
|CLK_I||IN||1||Main clock input|
|Avalon Slave Interface|
|AVALON_WRITEDATA_I||IN||32||Slave write data bus|
|AVALON_WRITE_I||IN||1||Slave write data request|
|AVALON_READ_I||IN||1||Slave read data request|
|AVALON_ADDRESS_I||IN||2||Slave address bus|
|AVALON_READDATA_O||OUT||32||Slave read data bus|
|Avalon Master Interface|
|AVALON_MASTER_WAITREQUEST||IN||1||Master wait request signal|
|AVALON_MASTER_ADDRESS_O||OUT||32||Master address bus|
|AVALON_MASTER_BYTEENABLE_O||OUT||2||Master byte enable signals|
|AVALON_MASTER_WRITEDATA_O||OUT||16||Master write data bus|
|ADC_DB_IO||I/O||16||ADC bidirectional data bus used to write/read data to/from the AD7671 eval board.|
|ADC_BUSY_I||IN||1||Busy Input. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data-ready clock signal.|
|ADC_CS_N_O||OUT||1||Chip Select. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled. CS is also used to gate the external serial clock.|
|ADC_RD_N_O||OUT||1||Read Data. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.|
|ADC_WR_N_O||OUT||1||Used manually configure the AD7671 evaluation board, by writing the internal registers of the FPGA.|
|ADC_CONTROL_O||OUT||1||Used to select between stand-alone mode or manually configure the AD7671 evaluation board|
|ADC_ADDR_O||OUT||3||Used to manually configure the AD7671 evaluation board by writing the internal registers of the FPGA.|
|ADC_RESET_O||OUT||1||Used to reset the evaluation board|
|Table 2 Port description|
Table 3 describes the registers of the Avalon peripheral:
|CONTROL_REGISTER||0||32||RW|| Bit 0 is used to start data acquisition
Bit 1 is used to initiate software reset of the core
Bit 2 is used to configure the Avalon write master core to write data to the same location
Bit 3 is used to write data to the AD7671 evaluation board
Bit 4 is used to drive the CONTROL pin of the EVAL board
|ACQ_COUNT_REGISTER||1||32||RW||Register used to configure the number of samples to be acquired when acquisition is started|
|BASE_REGISTER||2||32||RW||Register used to configure the base address of the memory location where the acquired data is to be written|
|STATUS||3||32||R|| Bit 0 is used to signal that the acquisition is complete
Bit 1 is used to signal that the internal memory buffer has been overflown
Bit 2 is used to signal that the user has performed a read of an unavailable register
|DUT_WRITE_REGISTER||4||32||W||Register used to perform writes on the device under test. Bits[15:0] are used for data and [18:16] are used as address. The rest are discarded|
|Table 3 Register description|
The follwing figure presents the timing diagram for the read operations from the AD7671 core.
The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load into the FPGA an image that contains a fully functional system. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder. Now the FPGA contains a fully functional system and it is possible to skip directly to the Evaluation Project User Interface section of this document.
This section presents the steps for developing a software application that will run on the CED1Z system and will be used for controlling and monitoring the operation of the ADI evaluation board.
Launch the Nios II SBT from the Start → All Programs → Altera → Nios II EDS 11.0 → Nios II 11.0 Software Build Tools for Eclipse (SBT).
NOTE: Windows 7 users will need to right-click and select Run as administrator. Another method is to right-click and select Properties and click on the Compatibility tab and select the Run This Program As An Administrator checkbox, which will make this a permanent change.
The tool will create two new software project directories. Each Nios II application has 2 project directories in the Eclipse workspace.
Since you chose the blank project template, there are no source files in the application project directory at this time. The BSP contains a directory of software drivers as well as a system.h header file, system initialization source code and other software infrastructure.
The software project provided in this lab does not make use of an operating system. All stdout, stdin and stderr messages will be directed to the jtag_uart.
The memory used by the design is should be changed from OnChip ram to SRAM for the .text region.
In addition to the board support package settings configured using the BSP Editor, there are other compilation settings managed by the Eclipse environment such as compiler flags and optimization level.
In Windows Explorer locate the project directory which contains a directory called Software. In Windows Explorer select all the files and directories from the Software folder and drag and drop them into the Eclipse software project ADIEvalBoard.
Just as you configured the optimization level for the BSP project, you should set the optimization level for the application software project ADIEvalBoard as well.
Application code can be conveniently organized in a directory structure. This section shows how to define these paths in the makefile.
These 2 steps will compile and build the associated board support package, then the actual application software project itself. The result of the compilation process will be an Executable and Linked Format (.elf) file for the application, the ADIEvalBoard.elf file.
In case an error appears at compile time with a description like : section .rodata loaded at [00400164,00400477] overlaps section .text loaded at [00400164,004054d7] the enable_alt_load_copy_exceptions option must be unchecked from BSP Editor → Main → Settings → Advanced→ hal.linker
The CED1Z hardware is designed with a System ID peripheral. This peripheral is assigned a unique value based on when the hardware design was last modified in the SOPC Builder tool. SOPC Builder also places this information in the .sopcinfo hardware description file. The BSP is built based on the information in the .sopcinfo file.
To run the software project on the Nios II processor:
The code size and start address might be different than the ones displayed in the above screenshot.
In order to capture data from the ADC the following steps must be performed:
Note: If several consecutive data acquisitions are performed the captured data is appended to the Acquisition.csv file.