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resources:fpga:altera:ced1z:ad7626 [06 Sep 2012 09:12] – Specified explicitly that the driver is for Echoed-clock mode. Adrian Costinaresources:fpga:altera:ced1z:ad7626 [05 Nov 2012 17:25] (current) – Updated the quick evaluation section with procedure on how to reprogram the Evaluation Board Adrian Costina
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 ====== Quick Evaluation ====== ====== Quick Evaluation ======
-{{page>:resources:fpga:altera:ced1z:quick_evaluation}}+ 
 +The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder. 
 + 
 +The Evaluation Board design presented on this page is different than the default design loaded on the AD7626EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat: 
 +  * 1. Connect the USB-Blaster to the P2 port 
 +  * 2. Start Quartus II, Start Tools ->Programmer 
 +  * 3. Select Mode Active Serial Programming 
 +  * 4. Press Add File and select EvalBoardFPGA\AD7626.pof 
 +  * 5. Check Program/Configure and Press Start. 
 +  * 6. After the programming ends, power off the CED1Z and reprogramm it using program_fpga.bat as described above. 
 + 
 +In order to acquire data, follow the instructions in the //**Evaluation Project Data Acquisition**// section.
  
 ====== NIOS II Software Design ====== ====== NIOS II Software Design ======
 {{page>:resources:fpga:altera:ced1z:common_software_design}} {{page>:resources:fpga:altera:ced1z:common_software_design}}
  
-====== Evaluation Project User Interface ======+====== Evaluation Project Data Acquisition ======
  
 In order to capture data from the ADC the following steps must be performed: In order to capture data from the ADC the following steps must be performed:
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   * [[ez>community/fpga|ask questions about the FPGA reference design]]   * [[ez>community/fpga|ask questions about the FPGA reference design]]
   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
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resources/fpga/altera/ced1z/ad7626.txt · Last modified: 05 Nov 2012 17:25 by Adrian Costina