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--- resources:fpga:altera:bemicro:common [14 Sep 2011 16:50] – [Create a new project using the NIOS II Software Build Tools for Eclipse] Andrei Cozma
+++ resources:fpga:altera:bemicro:common [03 Jan 2013 20:42] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
-====== Getting Started ======
-The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
-===== Hardware Items =====
-Below is presented the list of required hardware items:
-  * Arrow Electronics [[http://www.arrow.com/bemicrosdk/|BeMicro SDK]] FPGA-based MCU Evaluation Board
-  * [[http://www.arrownac.com/solutions/adi_interposer/|BeMicro SDK/SDP Interposer]] adapter board
-  * ADI Device evaluation board
-  * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory
-===== Software Tools =====
-Below is presented the list of required software tools:
-  * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0
-  * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool
-  * Lab Design Files
-The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web.
-The **Micrium uC/Probe Trial** version is available via download from the web at [[http://micrium.com/download/Micrium-uC-Probe-Setup-Trial.exe]].  After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list.
-===== Extract the Lab Files =====
-Create a folder called “**//ADIEvalBoardsLab//**” on your PC and extract the **//ADIEvalBoardsDemo.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoardsLab//** folder: **//FPGA//**, **//Software//**, **//ucProbeInterface//**. An optional //**HDL**// folder can be also present to store the HDL code for the NIOS II peripherals needed to communicate with the evaluation board.
-{{ :resources:fpga:altera:bemicro:image005.png?500 }}
-===== Install the USB-Blaster Device Driver =====
-After the **Quartus II** and **Nios II** software packages are installed, you can plug the BeMicro SDK board into your USB port. Your Windows PC will find the new hardware and try to install the driver.
-{{ :resources:fpga:altera:bemicro:image007.png }}
-Since Windows cannot locate the driver for the device the automatic installation will fail and the driver has to be installed manually. In the //Device Manager// right click on the **USB-Blaster** device and select **//Update Driver Software//**.
-{{ :resources:fpga:altera:bemicro:image009.png?500 }}
-In the next dialog box select the option **//Browse my computer for driver software//**. A new dialog will open where it is possible to point to the driver’s location. Set the location to **altera\11.0\quartus\drivers\usb-blaster** and press **//Next//**.
-{{:resources:fpga:altera:bemicro:image011.png?400}}{{:resources:fpga:altera:bemicro:image013.png?400}}
-<WRAP clear></WRAP>
-<note tip>If Windows presents you with a message that the drivers have not passed Windows Logo testing, please click “**//Install this driver software anyway//**”. Upon installation completion a message will be displayed to inform that the installation is finished.</note>
-{{:resources:fpga:altera:bemicro:image017.png?400}}{{:resources:fpga:altera:bemicro:image016.jpg?400}}
-====== FPGA Design ======
-The lab is delivered together with a set of design files that are used to evaluate the ADI part. The FPGA image that must be loaded into the BeMicroSDK FPGA is included in the design files. This section presents the components included in the FPGA image and also the procedure to load the image into the FPGA.
-===== FPGA Components =====
-The following components are implemented in the FPGA design:
-^ Name           ^ Address         ^ IRQ       ^ Remarks ^
-| CPU            | 800             | -         |         |
-| Main PLL       | 80              | -         |         |
-| JTAG UART      | 90              | 0         |         |
-===== Load the FPGA Image =====
-To load the FPGA image the following steps must be performed:
-  * Plug in the **BeMicroSDK** Stick into a USB port
-  * Start **Altera Quartus Web edition** and start the programmer by selecting the menu option //**Tools->Programmer**//
-  * Select **//Add File//** and select the file **//ADIEvalBoardsLab/FPGA/SDP1_bemicro2.jic//**
-  * Check the //**Program/Configure**// box and press **//Start//**
-{{ :resources:fpga:altera:bemicro:image020.jpg?400 }}
-After finishing, the image is permanently loaded to the configuration Flash and the system will start with a
-blinking LED after reset or power up.
-====== NIOS II Software Design ======
 This section presents the steps for developing a software application that will run on the **BeMicroSDK** system and will be used for controlling and monitoring the operation of the ADI evaluation board.
@@ Line 92: / Line 6: @@
 Launch the **Nios II SBT** from the **//Start -> All Programs -> Altera -> Nios II EDS 11.0 -> Nios II 11.0
 Software Build Tools for Eclipse (SBT)//**.
-<note tip>NOTE: Windows 7 users will need to right-click and select **//Run as administrator//**. Another method is to right-click and select **//Properties//** and click on the //**Compatibility**// tab and select the **//Run This Program As An Administrator//** checkbox, which will make this a permanent change.</note>
+<WRAP tip>NOTE: Windows 7 users will need to right-click and select **//Run as administrator//**. Another method is to right-click and select **//Properties//** and click on the //**Compatibility**// tab and select the **//Run This Program As An Administrator//** checkbox, which will make this a permanent change.</WRAP>
 === 1. Initialize Eclipse workspace ===
-When Eclipse first launches, a dialog box appears asking what directory it should use for its workspace. It is useful to have a separate Eclipse workspace associated with each hardware project that is created in SOPC Builder.
+  * When Eclipse first launches, a dialog box appears asking what directory it should use for its workspace. It is useful to have a separate Eclipse workspace associated with each hardware project that is created in SOPC Builder. Browse to the **//ADIEvalBoardLab//** directory and click //**Make New Folder**// to create a folder for the software project. Name the new folder “//**eclipse_workspace**//”. After selecting the workspace directory, click **//OK//** and Eclipse will launch and the workbench will appear in the **//Nios II//** perspective.
-Browse to the **//ADIEvalBoardsLab//** directory and click //**Make New Folder**// to create a folder for the software project. Name the new folder “//**eclipse_workspace**//”. After selecting the workspace directory, click **//OK//** and Eclipse will launch and the workbench will appear in the **//Nios II//** perspective.
-{{:resources:fpga:altera:bemicro:image023.png?350}}{{:resources:fpga:altera:bemicro:image022.jpg?350}}
+{{ :resources:fpga:altera:bemicro:eclipseworkspace.png?500 }}
-==== Create a new software project in the SBT ====
+=== 2. Create a new software project in the SBT ===
-  * Select File -> New -> Nios II Application and BSP from Template.
+  * Select **//File -> New -> Nios II Application and BSP from Template//**.
-{{ :resources:fpga:altera:bemicro:image025.png?300 }}
+{{ :resources:fpga:altera:bemicro:image025.png?400 }}
-  * Click the Browse button in the SOPC Information File Name dialog box.
+  * Click the **//Browse//** button in the **//SOPC Information File Name//** dialog box.
-  * Select the uC.sopcinfo file located in the AdEvalBoardsLab/FPGA directory.
+  * Select the **//uC.sopcinfo//** file located in the **//ADIEvalBoardLab/FPGA//** directory.
-  * Set the name of the Application project to “AdEvalBoardsDemo”.
+  * Set the name of the Application project to “**//ADIEvalBoard//**”.
-  * Select the Blank Project template under Project template.
+  * Select the **//Blank Project//** template under **//Project template//**.
-  * Click the Finish button.
+  * Click the **//Finish//** button.
-{{ :resources:fpga:altera:bemicro:image027.png?300 }}
+{{ :resources:fpga:altera:bemicro:eclipseblankproject.png?400 }}
 The tool will create two new software project directories. Each Nios II application has 2 project directories in the Eclipse workspace.
   * The application software project itself - this where the application lives.
-  * The second is the Board Support Package (BSP) project associated with the main application software project. This project will build the system library drivers for the specific SOPC system. This project inherits the name from the main software project and appends “_bsp” to that.
+  * The second is the **//Board Support Package (BSP)//** project associated with the main application software project. This project will build the system library drivers for the specific SOPC system. This project inherits the name from the main software project and appends “**//_bsp//**” to that.
-{{ :resources:fpga:altera:bemicro:image029.png?300 }}
+{{ :resources:fpga:altera:bemicro:eclipseprojects.png?300 }}
-Since you chose the “blank” project template, there are no source files in the application project directory at this time. The BSP contains a directory of software drivers as well as a system.h header file, system initialization source code and other software infrastructure.
+Since you chose the blank project template, there are no source files in the application project directory at this time. The BSP contains a directory of software drivers as well as a system.h header file, system initialization source code and other software infrastructure.
 ===== Configure the Board Support Package =====
-  * Configure the board support package to specify the properties of this software system by using the BSP Editor tool. These properties include what interface should be used for stdio and stderr messages, the memory in which stack and heap should be allocated and whether an operating system or network stack should be included with this BSP.
+  * Configure the board support package to specify the properties of this software system by using the **//BSP Editor//** tool. These properties include what interface should be used for //stdio// and //stderr// messages, the memory in which stack and heap should be allocated and whether an operating system or network stack should be included with this BSP.
-  * Right click on the AdEvalBoardsDemo_bsp project and select Nios II -> BSP Editor… from the right-click menu.
+  * Right click on the **//ADIEvalBoard_bsp//** project and select **//Nios II -> BSP Editor…//** from the right-click menu.
-{{ :resources:fpga:altera:bemicro:image031.png?300 }}
+{{ :resources:fpga:altera:bemicro:eclipsebspmenu.png?400 }}
-The software project provided in this lab does not make use of an operating system. All stdout, stdin and stderr messages will be directed to the jtag_uart.
+The software project provided in this lab does not make use of an operating system. All //stdout//, //stdin// and //stderr// messages will be directed to the //jtag_uart//.
-  * Select the “Common” settings view. In the “Common” settings view, change the following settings:
+  * Select the **//Common//** settings view. In the **//Common//** settings view, change the following settings:
-    * Select the jtag_uart for stdin, stdout and stderr messages. Note that you have more than one choice.
+    * Select the //**jtag_uart**// for //stdin//, //stdout// and //stderr// messages. Note that you have more than one choice.
-    * Select none for the sys_clk_timer and timestamp_timer.
+    * Select **//none//** for the //sys_clk_timer// and //timestamp_timer//.
-{{ :resources:fpga:altera:bemicro:image033.png?300 }}
+{{ :resources:fpga:altera:bemicro:image033.png?500 }}
-  * Select File -> Save to save the board support package configuration to the settings.bsp file.
+  * Select **//File -> Save//** to save the board support package configuration to the //settings.bsp// file.
-  * Click the Generate button to update the BSP.
+  * Click the **//Generate//** button to update the BSP.
-  * When the generate has completed, select File -> Exit to close the BSP Editor.
+  * When the generate has completed, select **//File -> Exit//** to close the BSP Editor.
 ===== Configure BSP Project Build Properties =====
-In addition to the board support package settings configured using the BSP Editor, there are other compilation settings managed by the Eclipse environment such as compiler flags and optimization level.
+In addition to the board support package settings configured using the **//BSP Editor//**, there are other compilation settings managed by the Eclipse environment such as compiler flags and optimization level.
-  * Right click on the AdEvalBoardsDemo_bsp software project and select Properties from the right-click menu.
+  * Right click on the **//ADIEvalBoard_bsp//** software project and select **//Properties//** from the right-click menu.
-  * On the left-hand menu, select Nios II BSP Properties.
+  * On the left-hand menu, select **//Nios II BSP Properties//**.
-  * During compilation, the code may have various levels of optimization which is a tradeoff between code size and performance. Change the Optimization level setting to Level 2
+  * During compilation, the code may have various levels of optimization which is a tradeoff between code size and performance. Change the **//Optimization level//** setting to **//Level 2//**
-  * Since our software does not make use of C++, uncheck “Support C++”.
+  * Since our software does not make use of C++, uncheck **//Support C++//**.
-  * Press Apply and OK to regenerate the BSP and close the Properties window.
+  * Check the **//Reduced device drivers//** option
+  * Check the **//Small C library//** option
+  * Press **//Apply//** and **//OK//** to regenerate the BSP and close the **//Properties//** window.
-{{ :resources:fpga:altera:bemicro:image035.png?300 }}
+{{ :resources:fpga:altera:bemicro:eclipsebspproperties.png?500 }}
 ===== Add source code to the project =====
-In Windows Explorer locate the project directory which contains a directory called “Software”. In Windows Explorer select all the files and directories from the Software folder and drag and drop them into the Eclipse software project AdEvalBoardsDemo.
+In Windows Explorer locate the project directory which contains a directory called **//Software//**. In Windows Explorer select all the files and directories from the **//Software//** folder and drag and drop them into the Eclipse software project **//ADIEvalBoard//**.
-  * Select all the files and folders and drag them over the AdEvalBoardsDemo project in the SBT window and drop the files onto the project folder.
+  * Select all the files and folders and drag them over the **//ADIEvalBoard//** project in the SBT window and drop the files onto the project folder.
-{{ :resources:fpga:altera:bemicro:image037.png?300 }}
+{{ :resources:fpga:altera:bemicro:eclipsecopyfiles.png?600 }}
-  * A dialog box will appear to select the desired operation. Select the option Copy files and folders and press OK.
+  * A dialog box will appear to select the desired operation. Select the option **//Copy files and folders//** and press **//OK//**.
-{{ :resources:fpga:altera:bemicro:image039.png?300 }}
+{{ :resources:fpga:altera:bemicro:image039.png?400 }}
   * This should cause the source files to be physically copied into the file system location of the software project directory and register these source files within the Eclipse workspace so that they appear in the Project Explorer file listing.
-{{ :resources:fpga:altera:bemicro:image041.png?300 }}
+{{ :resources:fpga:altera:bemicro:eclipseprojectfiles.png?300 }}
 ===== Configure Application Project Build Properties =====
-Just as you configured the optimization level for the BSP project, you should set the optimization level for the application software project AdEvalBoardsDemo as well.
+Just as you configured the optimization level for the BSP project, you should set the optimization level for the application software project **//ADIEvalBoard//** as well.
-  * Right click on the AdEvalBoardsDemo software project and select Properties from the right-click menu.
+  * Right click on the **//ADIEvalBoard//** software project and select **//Properties//** from the right-click menu.
-  * On the left-hand menu, select the Nios II Application Properties tab
+  * On the left-hand menu, select the **//Nios II Application Properties//** tab
-  * Change the Optimization level setting to Level 2.
+  * Change the **//Optimization level//** setting to **//Level 2//**.
-  * Press Apply and OK to save the changes.
+  * Press **//Apply//** and **//OK//** to save the changes.
-{{ :resources:fpga:altera:bemicro:image043.png?300 }}
+{{ :resources:fpga:altera:bemicro:eclipseprojproperties.png?500 }}
 ===== Define Application Include Directories =====
 Application code can be conveniently organized in a directory structure. This section shows how to define these paths in the makefile.
-  * In the Eclipse environment double click on “my_include_paths.in” to open the file.
+  * In the Eclipse environment double click on **//my_include_paths.in//** to open the file.
-  * Click the Ctrl and A keys to select all the text. Click the Ctrl and C keys to copy all the text.
+  * Click the **//Ctrl//** and **//A//** keys to select all the text. Click the //**Ctrl**// and **//C//** keys to copy all the text.
-{{ :resources:fpga:altera:bemicro:image045.png?300 }}
+{{ :resources:fpga:altera:bemicro:eclipsemyinclude.png?400 }}
-  * Double click on “Makefile” to open the file.
+  * Double click on **//Makefile//** to open the file.
-  * If you see the message shown here about resources being out of sync, right click on the Makefile and select Refresh.
+  * If you see the message shown here about resources being out of sync, right click on the **//Makefile//** and select **//Refresh//**.
-{{ :resources:fpga:altera:bemicro:image048.gif?300 }}
+{{ :resources:fpga:altera:bemicro:eclipsemakefileoutofdate.png?400 }}
-  * Select line “ APP_INCLUDE_DIRS :=”
+  * Select the line **APP_INCLUDE_DIRS :=**
-{{ :resources:fpga:altera:bemicro:image049.png?300 }}
+{{ :resources:fpga:altera:bemicro:image049.png?500 }}
-  * Click the Ctrl and V keys to replace the selected line with the include paths.
+  * Click the **//Ctrl//** and **//V//** keys to replace the selected line with the include paths.
-{{ :resources:fpga:altera:bemicro:image051.png?300 }}
+{{ :resources:fpga:altera:bemicro:image051.png?500 }}
-  * Click the Ctrl and S keys to save the Makefile.
+  * Click the **//Ctrl//** and **//S//** keys to save the **//Makefile//**.
 ===== Compile, Download and Run the Software Project =====
-===== Build the Application and BSP Projects =====
+=== 1. Build the Application and BSP Projects ===
-  * Right click the AdEvalBoardsDemo_bsp software project and choose Build Project to build the board support package.
+  * Right click the **//ADIEvalBoard_bsp//** software project and choose **//Build Project//** to build the board support package.
-  * When that build completes, right click the AdEvalBoardsDemo application software project and choose Build Project to build the Nios II application.
+  * When that build completes, right click the **//ADIEvalBoard//** application software project and choose **//Build Project//** to build the Nios II application.
-These 2 steps will compile and build the associated board support package, then the actual application software project itself. The result of the compilation process will be an Executable and Linked Format file for the application, the AdEvalBoardsDemo.elf file.
+These 2 steps will compile and build the associated board support package, then the actual application software project itself. The result of the compilation process will be an //Executable and Linked Format (.elf)// file for the application, the **//ADIEvalBoard.elf//** file.
-{{:resources:fpga:altera:bemicro:image053.png?300}}{{:resources:fpga:altera:bemicro:image056.jpg?300}}
+{{:resources:fpga:altera:bemicro:eclipsebuildbsp.png?400}}
+{{:resources:fpga:altera:bemicro:eclipsebuildproj.png?400}}
-===== Verify the Board Connection =====
+=== 2. Verify the Board Connection ===
-The BeMicroSDK hardware is designed with a System ID peripheral. This Peripheral is assigned a unique value based on when the hardware design was last modified in the SOPC Builder tool. SOPC Builder also places this information in the .sopcinfo hardware description file. The BSP is built based on the information in the .sopcinfo file.
+The **BeMicroSDK** hardware is designed with a //System ID// peripheral. This peripheral is assigned a unique value based on when the hardware design was last modified in the SOPC Builder tool. SOPC Builder also places this information in the //.sopcinfo// hardware description file. The BSP is built based on the information in the //.sopcinfo// file.
-  * Select the AdEvalBoardsDemo application software project.
+  * Select the **//ADIEvalBoard//** application software project.
-  * Select Run -> Run Configurations…
+  * Select **//Run -> Run Configurations…//**
-  * Select the Nios II Hardware hardware configuration type.
+  * Select the **//Nios II Hardware//** configuration type.
-  * Press the New Button to create a new configuration.
+  * Press the **//New//** button to create a new configuration.
-  * Change the configuration name to BeMicroSDK and click Apply.
+  * Change the configuration name to **//BeMicroSDK//** and click **//Apply//**.
-  * On the Target Connection tab, press the Refresh Connections button. You may need to expand the window or scroll to the right to see this button.
+  * On the **//Target Connection//** tab, press the **//Refresh Connections//** button. You may need to expand the window or scroll to the right to see this button.
-  * Select the jtag_uart_1 as the Byte Stream Device for stdio.
+  * Select the **//jtag_uart//** as the **//Byte Stream Device//** for //stdio//.
-  * Check the Ignore mismatched system ID option.
+  * Check the **//Ignore mismatched system ID option//**.
-  * Check the Ignore mismatched system timestamp option.
+  * Check the **//Ignore mismatched system timestamp option//**.
-{{ :resources:fpga:altera:bemicro:image061.png?300 }}
+{{:resources:fpga:altera:bemicro:eclipserunconfig.png?400}}
+{{:resources:fpga:altera:bemicro:image059.png?400}}
-===== Run the Software Project on the Target =====
+{{ :resources:fpga:altera:bemicro:ignoreid.png?500 }}
+=== 3. Run the Software Project on the Target ===
 To run the software project on the Nios II processor:
-  * Press the Run button in the Run Configurations window.
+  * Press the **//Run//** button in the **//Run Configurations//** window.
-This will re-build the software project to create an up–to-date executable and then download the code into memory on the BeMicroSDK hardware. The debugger resets the Nios II processor, and it executes the downloaded code. Note that the code is verified in memory before it is executed.
-{{ :resources:fpga:altera:bemicro:image063.png?300 }}
-Note: The code size and start address might be different than the ones displayed in the above screenshot.
-====== uC-Probe Interface ======
-A notable challenge in embedded systems development is to overcome the lack of feedback that such systems typically provide. Many developers resort to blinking LEDs or instrumenting their code with printf() in order to determine whether or not their systems are running as expected. Micrium provides a unique tool named μC-Probe to assist these developers. With this tool, developers can effortlessly read and write the variables on a running embedded system.
-This section presents the steps required to install the Micrium uC-Probe software tool and to run the demonstration project for the EVAL-ADN2850SDZ evaluation board. A description of the uC-Probe demonstration interface is provided.
-===== Configure uC-Probe =====
-Launch uC-Probe from the Start -> All Programs -> Micrium -> uC-Probe.
-Select uC-Probe options.
-  * Click on the uC-Probe icon on the top left portion of the screen.
-  * Click on the options button to open the dialog box
-{{ :resources:fpga:altera:bemicro:image066.gif?300 }}
-Set target board communication protocol as JTAG UART
-  * Click on the Communication Tab icon on the top left portion of the dialog box
-  * Select the JTAG UART pilot button.
-{{ :resources:fpga:altera:bemicro:image067.png?300 }}
-Setup JTAG UART communication settings
-  * Select the JTAG-UART option.
-  * Press the Open File button to select the JTAG Debug Information file (.jdi)
-  * Navigate to the AdEvalBoardLab/FPGA folder and select the BeMicroSDK.jdi file. Press Open.
-  * Type the value 1 in the the Device Id window.
-{{:resources:fpga:altera:bemicro:image070.jpg?300}}{{:resources:fpga:altera:bemicro:image071.png?300}}
-  * Select uCProbe_uart(0) from the Instance Id pulldown menu.
-{{ :resources:fpga:altera:bemicro:image073.png?300 }}
-  * Press Apply and OK to exit the options menu. The embedded target has two UARTs. uCProbe will be communicating with the uCProbe_uart.
-===== Load and Run the Demonstration Project =====
-  * Click the Open option from the uC-Probe menu and select the file AdEvalBoardLab/ucProbeInterface/AD2850_Interface.wsp.
+This will re-build the software project to create an up–to-date executable and then download the code into memory on the **BeMicroSDK** hardware. The debugger resets the Nios II processor, and it executes the downloaded code. Note that the code is verified in memory before it is executed.
-{{:resources:fpga:altera:bemicro:image077.png?300}}{{:resources:fpga:altera:bemicro:image076.jpg?300}}
+{{ :resources:fpga:altera:bemicro:image063.png?400 }}
-  * Before opening the interface uC-Probe will ask for a symbols file that must be associated with the interface. Select the file AdEvalBoardsLab/FPGA/software/AdEvalBoardsDemo/AdEvalBoards.elf to be loaded as a symbol file.
-{{ :resources:fpga:altera:bemicro:image080.jpg?300 }}
+<WRAP round help>The code size and start address might be different than the ones displayed in the above screenshot.</WRAP>
-  * Run the demonstration project by pressing the uC-Probe Play button.
-{{ :resources:fpga:altera:bemicro:image081.png?300 }}

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