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resources:fpga:altera:bemicro:ad7984 [28 Sep 2012 09:22]
AdrianC Added common section for describing the evaluation setup and System Demonstration Platform
resources:fpga:altera:bemicro:ad7984 [12 Oct 2012 11:48]
ACozma [AD7984 Evaluation Project Overview]
Line 106: Line 106:
 | ADC_CLK_I ​                | IN  | 1  | Clock to be sent to the ADC during the conversion process. | | ADC_CLK_I ​                | IN  | 1  | Clock to be sent to the ADC during the conversion process. |
 | //**IP control and data ports**// |||| | //**IP control and data ports**// ||||
-| DATA_O ​                   | OUT | 16 | Outputs the data read from the ADC. The channel ID is stored on the 4 most significant bits and the read data is stored on the 12 least significant bits. If the ADC is driven in word read mode then the channel ID will always be 0. |+| DATA_O ​                   | OUT | 18 | Outputs the data read from the ADC. |
 | DATA_RD_READY_O ​          | OUT | 1  | Active high signal to indicate the status of a read operation from the AD7984. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. | | DATA_RD_READY_O ​          | OUT | 1  | Active high signal to indicate the status of a read operation from the AD7984. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. |
 | //**AD7984 control and data ports**// |||| | //**AD7984 control and data ports**// ||||
resources/fpga/altera/bemicro/ad7984.txt · Last modified: 12 Oct 2012 11:48 by ACozma