This lab presents the steps to setup an environment for using the EVAL-AD7683SDZ evaluation board together with the BeMicro SDK USB stick and the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7683SDZ Evaluation Board with the BeMicro SDK Platform.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD7683SDZ Evaluation Board.
The EVAL-AD7683SDZ evaluation board is a member of a growing number of boards available for the SDP. It was designed to help customers evaluate performance or quickly prototype new AD7683 circuits and reduce design time.
The AD7683 is a 16-bit, charge redistribution, successive approximation, PulSAR® analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.7 V and 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes (B grade), an internal conversion clock, and a serial, SPI-compatible interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CS falling edge, it samples an analog input, +IN, between 0 V to REF with respect to a ground sense, –IN. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Below is presented the list of required hardware items:
Below is presented the list of required software tools:
The Quartus II design software and the Nios II EDS is available via the Altera Complete Design Suite DVD or by downloading from the web.
Create a folder called “ADIEvalBoardLab” on your PC and extract the ad7683_evalboardlab.zip archive to this folder. Make sure that there are NO SPACES in the directory path. After extracting the archive the following folders should be present in the ADIEvalBoardLab folder: FPGA, Hdl Software, DataCapture, NiosCpu.
|FPGA|| Contains all the files necessary to program the BeMicro FPGA board in order to run the evaluation project. By executing the script program_fpga.bat the FPGA will be programmed with the evaluation project. New NIOS II applications can be created using the files from this folder.
The ip subfolder contains the AD7683 NIOS II peripheral's source code.
|Hdl|| Contains the source files for the AD7683 HDL driver:
- The doc subfolder contains a brief documentation for the driver.
- The src subfolder contains the HDL source files.
- The tb folder contains the sources of the driver's testbench.
|NiosCpu||Contains the Quartus evaluation project source files . The ip subfolder contains the AD7683 Nios2 peripheral source code.|
|Software||Contains the source files of the Nios2 SBT evaluation project.|
|DataCapture||Contains the script files used for data acquisition|
After the Quartus II and Nios II software packages are installed, you can plug the BeMicro SDK board into your USB port. Your Windows PC will find the new hardware and try to install the driver.
Since Windows cannot locate the driver for the device the automatic installation will fail and the driver has to be installed manually. In the Device Manager right click on the USB-Blaster device and select Update Driver Software.
In the next dialog box select the option Browse my computer for driver software. A new dialog will open where it is possible to point to the driver’s location. Set the location to altera\<version number>\quartus\drivers\usb-blaster and press Next.
If Windows presents you with a message that the drivers have not passed Windows Logo testing, please click “Install this driver software anyway”. Upon installation completion a message will be displayed to inform that the installation is finished.
The evaluation project contains all the source files needed to build a system that can be used to configure the AD7683 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the BeMicro board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the onchip RAM of the BeMicro board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis.
The following components are implemented in the FPGA design:
|EPCS FLASH CONTROLLER||0x00001800||2|
|Table 1 System components|
The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the onchip RAM, a module which implements an Avalon master interface which is used to write data directly in the onchip RAM and a module which is the actual driver of the DUT. The driver can also be used as standalone in FPGA designs which do not contain a softcore. Following is presented a block diagram of the HDL driver and a description of the driver's interface signals.
Table 2 describes the ports of the AD7683 HDL driver.
|Clock and reset ports|
|FPGA_CLK_I||IN||1||Main clock input.|
|RESET_I||IN||1||Active low reset signal.|
|IP control and data ports|
|DATA_O||OUT||16||Outputs the data read from the ADC.|
|DATA_RD_READY_O||OUT||1||Active high signal to indicate the status of a read operation from the AD7683. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus.|
|AD7683 control and data ports|
|ADC_DOUT_I||IN||1||ADC Serial Data Output. The conversion result is output on this pin. It is synchronized to SCLK|
|ADC_SCLK_O||OUT||1||ADC Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.|
|ADC_CS_N_O||OUT||1||On the falling edge, the ADC initiates the conversions. The part returns to shutdown mode as soon as the conversion is completed.|
|Table 2 AD7683 driver ports description|
The follwing figure presents the timing diagram for the read operations from the AD7683 driver.
Table 3 describes the ports of the Avalon peripheral:
|Clock and reset ports|
|CSI_SYSC_CLK_I||IN||1||Main clock input|
|Avalon Slave Interface|
|AVS_AVALONS_WRITEDATA_I||IN||32||Slave write data bus|
|AVS_AVALONS_WRITE_I||IN||1||Slave write data request|
|AVS_AVALONS_READ_I||IN||1||Slave read data request|
|AVS_AVALONS_ADDRESS_I||IN||3||Slave address bus|
|AVS_AVALONS_READDATA_O||OUT||32||Slave read data bus|
|Avalon Master Interface|
|AVM_AVALONM_WAITREQUEST_I||IN||1||Master wait request signal|
|AVM_AVALONM_ADDRESS_O||OUT||32||Master address bus|
|AVM_AVALONM_WRITE_O||OUT||1||Master write signal|
|AVM_AVALONM_BYTEENABLE_O||OUT||4||Master byte enable signals|
|AVM_AVALONM_WRITEDATA_O||OUT||32||Master write data bus|
|COE_ADC_DOUT_I||IN||1||ADC Serial Data Output. The conversion result is output on this pin. It is synchronized to SCLK|
|COE_ADC_SCLK_O||OUT||1||ADC Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.|
|COE_ADC_CS_N_O||OUT||1||On the falling edge, the ADC initiates the conversions. The part returns to shutdown mode as soon as the conversion is completed.|
|Table 3 Avalon peripheral ports description|
Table 4 describes the registers of the Avalon peripheral:
|CONTROL_REGISTER||0||32||RW|| Bit 0 is used to start data acquisition
Bit 1 is used to initiate software reset of the core
Bit 2 is used to configure the Avalon write master core to write data to the same location
Bit 3 is used to write data to the AD7683 evaluation board
|ACQ_COUNT_REGISTER||1||32||RW||Register used to configure the number of samples to be acquired when acquisition is started|
|BASE_REGISTER||2||32||RW||Register used to configure the base address of the memory location where the acquired data is to be written|
|STATUS_REGISTER||3||32||R|| Bit 0 is used to signal that the acquisition is complete
Bit 1 is used to signal that the internal memory buffer has been overflown
Bit 2 is used to signal that the user has performed a read of an unavailable register
|Table 4 Avalon peripheral registers description|
The next sections of this lab present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load into the FPGA an image that contains a fully functional system.The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image run the program_fpga.bat batch file located in the ADIEvalBoardLab/FPGA folder. After the image was loaded the system must be reset. Now the FPGA contains a fully functional system and it is possible to skip directly to the Demonstration Project User Interface section of this lab.
This section presents the steps for developing a software application that will run on the BeMicroSDK system and will be used for controlling and monitoring the operation of the ADI evaluation board.
Launch the Nios II SBT from the Start → All Programs → Altera 12.0sp2→ Nios II EDS 12.0sp2 → Nios II 12.0sp2 Software Build Tools for Eclipse (SBT).
NOTE: Windows 7 users will need to right-click and select Run as administrator. Another method is to right-click and select Properties and click on the Compatibility tab and select the Run This Program As An Administrator checkbox, which will make this a permanent change.
The tool will create two new software project directories. Each Nios II application has 2 project directories in the Eclipse workspace.
Since you chose the blank project template, there are no source files in the application project directory at this time. The BSP contains a directory of software drivers as well as a system.h header file, system initialization source code and other software infrastructure.
The software project provided in this lab does not make use of an operating system. All stdout, stdin and stderr messages will be directed to the jtag_uart.
In addition to the board support package settings configured using the BSP Editor, there are other compilation settings managed by the Eclipse environment such as compiler flags and optimization level.
In Windows Explorer locate the project directory which contains a directory called Software. In Windows Explorer select all the files and directories from the Software folder and drag and drop them into the Eclipse software project ADIEvalBoard.
Just as you configured the optimization level for the BSP project, you should set the optimization level for the application software project ADIEvalBoard as well.
These 2 steps will compile and build the associated board support package, then the actual application software project itself. The result of the compilation process will be an Executable and Linked Format (.elf) file for the application, the ADIEvalBoard.elf file.
The BeMicroSDK hardware is designed with a System ID peripheral. This peripheral is assigned a unique value based on when the hardware design was last modified in the SOPC Builder tool. SOPC Builder also places this information in the .sopcinfo hardware description file. The BSP is built based on the information in the .sopcinfo file.
To run the software project on the Nios II processor:
This will re-build the software project to create an up–to-date executable and then download the code into memory on the BeMicroSDK hardware. The debugger resets the Nios II processor, and it executes the downloaded code. Note that the code is verified in memory before it is executed.
The code size and start address might be different than the ones displayed in the above screenshot.
* Execute data_capture.bat script. At this point 8192 samples will be acquired at 99 KSPS from the ADC and saved into the BeMicro SDK memory. The data stored in the BeMicro SDK memory is transfered to the PC. After the data is transferred to the PC it is converted to 16 bit values.
Note: If several consecutive data acquisitions are performed the captured data is appended to the Acquisition.csv file.
In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: