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resources:fpga:altera:bemicro:ad5755 [05 Jan 2012 14:35] – Approved Andrei Cozmaresources:fpga:altera:bemicro:ad5755 [26 Jan 2021 01:21] (current) – update arrow links after their web site update Robin Getz
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 ====== Overview ====== ====== Overview ======
  
-This lab presents the steps to setup an environment for using the **[[adi>EVAL-AD5755SDZ]]** evaluation board together with the **[[http://www.arrownac.com/solutions/bemicro-sdk/|BeMicro SDK]]** USB stick, the Nios II Embedded Development Suite (EDS) and the [[http://micrium.com/page/products/tools/probe|Micrium μC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5755SDZ Evaluation Board with the BeMicro SDK Platform.+This lab presents the steps to setup an environment for using the **[[adi>EVAL-AD5755SDZ]]** evaluation board together with the **[[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]]** USB stick and the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD5755SDZ Evaluation Board with the BeMicro SDK Platform.
  
 {{ :resources:fpga:altera:bemicro:ad5755_bemicro.png?400 }} {{ :resources:fpga:altera:bemicro:ad5755_bemicro.png?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * an compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5755SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5755SDZ** Evaluation Board.
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   * [[adi>AD5755|AD5755 Product Info]] - pricing, samples, datasheet   * [[adi>AD5755|AD5755 Product Info]] - pricing, samples, datasheet
   * [[adi>/static/imported-files/user_guides/UG-244.pdf|EVAL-AD5755SDZ evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-244.pdf|EVAL-AD5755SDZ evaluation board user guide]]
-  * [[http://www.arrownac.com/solutions/bemicro-sdk|BeMicro SDK]]+  * [[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]]
   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 Below is presented the list of required hardware items: Below is presented the list of required hardware items:
-  * Arrow Electronics [[http://www.arrow.com/bemicrosdk/|BeMicro SDK]] FPGA-based MCU Evaluation Board +  * Arrow Electronics [[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]] FPGA-based MCU Evaluation Board 
-  * [[http://www.arrownac.com/solutions/adi_interposer/|BeMicro SDK/SDP Interposer]] adapter board+  * [[adi>sdp-bemicro|BeMicro SDK/SDP Interposer]] adapter board
   * **EVAL-AD5755SDZ** evaluation board   * **EVAL-AD5755SDZ** evaluation board
   * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory   * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory
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 Below is presented the list of required software tools: Below is presented the list of required software tools:
-  * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0 +  * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v13.0 
-  * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0 +  * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v13.0
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool +
-  * {{:resources:fpga:altera:bemicro:ad5755_evalboardlab.zip|Lab Design Files}}+
  
 The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web.  The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. 
  
-The **Micrium uC/Probe Trial** version is available via download from the web at [[http://micrium.com/download/Micrium-uC-Probe-Setup-Trial.exe]].  After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list. +After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list.
  
 +===== Downloads =====
 +  * {{:resources:fpga:altera:bemicro:ad5755_evalboardlab.zip|Lab Design Files}}
 ===== Extract the Lab Files ===== ===== Extract the Lab Files =====
  
-Create a folder called “**//ADIEvalBoardLab//**” on your PC and extract the **//ad5755_evalboardlab.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoardLab//** folder: **//FPGA//**, **//Software//**, **//ucProbeInterface//**, **//NiosCpu//**.+Create a folder called “**//ADIEvalBoardLab//**” on your PC and extract the **//ad5755_evalboardlab.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoardLab//** folder: **//FPGA//**, **//Software//**, **//NiosCpu//**.
  
-{{ :resources:fpga:altera:bemicro:labfolders.png?500 }}+{{ :resources:fpga:altera:bemicro:labfolder_console.png?500 }}
  
 ====== ====== ====== ======
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 ====== Quick Evaluation ====== ====== Quick Evaluation ======
-{{page>common_quick_eval}} 
  
-====== FPGA Design ====== +The next sections of this lab present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load into the FPGA an image that contains a fully functional system for the ADI platform evalution. 
-{{page>common_spi_i2c}}+The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the **Quartus II Web Edition** tool or the [[https://www.altera.com/download/programming/quartus2/pq2-index.jsp|Quartus II Programmer]] must be installed on your computer.
  
-====== NIOS II Software Design ====== +To load the FPGA image the first thing to do is to start a Nios2 Command Shell. To start the Nios II command shell on Windows platforms, on the Start menu, click ** All Programs **. On the **All Programs** menu, on the **Altera 13.0 Web Edition** submenu, on the **Nios II EDS 13.0** submenu, click ** Nios II 13.0 Command Shell **. The command shell is a Bourne-again shell (bash) with a pre-configured environment.
-{{page>common}}+
  
 +{{ :resources:fpga:altera:bemicro:nios2_cmd_shell.png?600 }}
  
-====== uC-Probe Interface ======+After the shell was started up, the first thing is to change the current path to project's directory path by typing the following command: 
  
-A notable challenge in embedded systems development is to overcome the lack of feedback that such systems typically provide. Many developers resort to blinking LEDs or instrumenting their code with //printf()// in order to determine whether or not their systems are running as expected. **Micrium** provides a unique tool named **μC-Probe** to assist these developers. With this tool, developers can effortlessly read and write the variables on a running embedded system. +** cd /cygdrive/<//Disk Label//>/<//Project Path//>/AD5755/Console ** and hit Enter.
-This section presents the steps required to install the **Micrium uC-Probe** software tool and to run the demonstration project for the ADI evaluation board. A description of the **uC-Probe** demonstration interface is provided.+
  
-===== Configure uC-Probe =====+{{ :resources:fpga:altera:bemicro:nios2_cmd_cd.png?600 }}
  
-Launch **uC-Probe** from the **//Start -> All Programs -> Micrium -> uC-Probe//**.+To configure the **BeMicroSDK** and run the software application have to run a bash script called program_bemicro.sh, this can be done by using the following command: **./program_bemicro.sh** and hit Enter. This script will configure the BeMicroSDK with the corresponding .sof file and will download and run the software application, and starts the stand-alone nios2-terminal.exe application. 
  
-Select **uC-Probe** options. +{{ :resources:fpga:altera:bemicro:nios2_cmd_program.png?500 }}
-  * Click on the **uC-Probe** icon on the top left portion of the screen. +
-  * Click on the **//Options//** button to open the dialog box.+
  
-{{ :resources:fpga:altera:bemicro:ucprobeoptionsbtn.png?300 }}+If the last message is ** AD5755 OK **, it means that the configuration was successful and the PC is connected to the device through JTAG-UART.
  
-Set target board communication protocol as **//JTAG UART//** +The **AD5755** support the following commands, which can used to evaluate the **AD5755** converter:
-  * Click on the **//Communication//** tab icon on the top left portion of the dialog box +
-  * Select the **//JTAG UART//** option.+
  
-{{ :resources:fpga:altera:bemicro:image067.png?400 }}+^ **Command** ^ **Description** ^ 
 +| **help?** | Display all available commands | 
 +| **register?** | Get register value for a specified channel, the command has two arguments: register address and channel | 
 +| **register=** | Set a register value, the command has four arguments: register type, which can be data or control, register address, channel number and the desired value | 
 +| **power?** | Display the power state of the dc-to-dc converters, DAC and internal amplifiers for the selected channel. The command has one argument : channel | 
 +| **power=** | Set up the power state of the dc-to-dc converters, DAC and internal amplifiers for the selected channel. The command has two arguments: channel and 1 for ON and 0 for OFF | 
 +| **range?** | Display the range of the selected channel. The command has one argument : channel | 
 +| **range=** | Set the range of the selected channel. Has two argument: channel and range | 
 +| **voltage?** | Display the output voltage of a specified channel. The command has one argument: channel | 
 +| **voltage=** | Set the output voltage of a specified channel. The command using two arguments: channel and the desired value | 
 +| **current?** | Display the output current of a specified channel. The command has one argument: channel | 
 +| **current=** | Set the output current of a specified channel. The command using two arguments: channel and the desired value |
  
-Setup **//JTAG UART//** communication settings +<WRAP tip>Note: When using the standalone nios2-terminal for interfacing with the AD5755, it might happen that no characters are echoed from the console, and the backspace are ignored. In this case should be used the Nios II Terminal Console windows from the Nios II IDE to evaluate the device.</WRAP>
-  * Select the **//JTAG-UART//** option from the **//Communication//** tab. +
-  * Press the **//Open File//** button to select the JTAG Debug Information file (**//.jdi//**) +
-  * Navigate to the **//ADIEvalBoardLab/FPGA//** folder and select the BeMicroSDK.jdi file. Press Open. +
-  * Type the value **//1//** in the the **//Device Id//** window.+
  
-{{ :resources:fpga:altera:bemicro:ucprobeoptionsjtag.png?400 }}+====== FPGA Design ====== 
 +{{page>common_spi_i2c_console}}
  
-  * Select **//uCProbe_uart(0)//** from the **//Instance Id//** pulldown menu.+====== NIOS II Software Design ====== 
 +{{page>common_console}}
  
-{{ :resources:fpga:altera:bemicro:image073.png?400 }} 
- 
-  * Press **//Apply//** and **//OK//** to exit the options menu. The embedded target has two UARTs. **uC-Probe** will be communicating with the **//uCProbe_uart//**. 
- 
-===== Load and Run the Demonstration Project ===== 
- 
-  * Click the **//Open//** option from the **uC-Probe** menu and select the file **//ADIEvalBoardLab/ucProbeInterface/AD5755_Interface.wsp//**. 
- 
-{{:resources:fpga:altera:bemicro:image077.png?400}}{{:resources:fpga:altera:bemicro:ad5755interfaceopen.png?400}} 
- 
-  * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the **Quick Evaluation** section, select the file **//ADIEvalBoardLab/ucProbeInterface/ADIEvalBoard.elf//** to be loaded as a symbol file, otherwise select the file **//ADIEvalBoardLab/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf//** to be loaded as a symbol file. 
- 
-{{ :resources:fpga:altera:bemicro:image080.jpg?400 }} 
- 
-  * Run the demonstration project by pressing the **//Play//** button. 
- 
-{{ :resources:fpga:altera:bemicro:image081.png?400 }} 
  
 ====== Demonstration Project User Interface ====== ====== Demonstration Project User Interface ======
  
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5755SDZ** evaluation board. +This section presents the UART Terminal Interface, which helps the user to interact with the software application, that will run on the BeMicroSDK. 
- +The UART Terminal Interface can be started in two different way. First from Nios II command shell, by using the **programm_fpga.sh** script (for quick evolution) or from Nios II IDE after programming the **BeMicroSDK**.
-{{ :resources:fpga:altera:bemicro:ad5755_interface.png?700 }} +
- +
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. +
- +
-**Section B** is used to select the DAC channel. +
-   +
-**Section C** is used to write data into the register selected by the Selection Slider. +
- +
-Options: +
- +
-  * Write to DAC data register (individual channel write). +
-  * Write to gain register (individual channel write). +
-  * Write to gain register (all DACs). +
-  * Write to offset register (individual channel write). +
-  * Write to offset register (all DACs) . +
-  * Write to clear code register (individual channel write). +
- +
- +
-**Section D** is used to read data from the register selected by the Selection Slider. +
- +
-Options: +
- +
-  * Read from DAC data register (individual channel read). +
-  * Read from DAC control register (individual channel read). +
-  * Read from Gain register (individual channel read). +
-  * Read from Offset register (individual channel read). +
-  * Read from Clear Code register (individual channel read). +
-  * Read from Slew Rate control register (individual channel read). +
-  * Read from Status register. +
-  * Read from Main control register. +
-  * Read from DC-to-DC control register. +
- +
-**Section E** is used to write data into the DAC n Control Register. +
- +
-Options: +
- +
-  * Internal – Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel.  +
-  * Clear – Clear enable bit. +
-  * Output – Enables/disables the selected output channel.  +
-  * Rset – Selects an internal or external current sense resistor for the selected DAC channel. +
-  * DC-DC – Powers the dc-to-dc converter on the selected channel. +
-  * OVRNG – Enables 20% overrange on voltage output channel only. No current output overrange available. +
-  * Output Range – Selects the output range to be enabled.  +
- +
-**Section F** is used to write data into the DC-DC Control Register. +
- +
-Options: +
- +
-  * DC-DC Comp – Selects between an internal and external compensation resistor for the dc-to-dc converter.  +
-  * Phase – User programmable dc-to-dc converter phase (between channels).  +
-  * Frequency – DC-to-dc switching frequency. +
-  * Max Voltage – Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter.  +
- +
-**Section G** is used to write data into the Main Control Register. +
- +
-Options: +
- +
-  * POC – The POC bit determines the state of the voltage output channels during normal operation. +
-  * StartRead – Enable status readback during a write. +
-  * EWD – Enable watchdog timer.  +
-  * WD Period – Select the timeout period for the watchdog timer. +
-  * ShtCctLim – Programmable short-circuit limit on the VOUT_x pin in the event of a short-circuit condition. +
-  * OutEn All – Enables the output on all four DACs simultaneously.  +
-  * DC-DC All – Powers up the dc-to-dc converter on all four channels simultaneously. +
- +
-**Section H** is used to write data into the Slew Rate Control Register. +
- +
-Options: +
- +
-  * SE – Enable SE. +
-  * SR Clock – Slew Rate Update Clock Options. +
-  * SR Step – Slew Rate Step Size Options.+
  
-**Section I** is used to write data into the Software Register.+<WRAP tip>Note: When using the standalone nios2-terminal for interfacing with the AD5755, it might happen that no characters are echoed from the console, and the backspace are ignored. In this case should be used the Nios II Terminal Console windows from the Nios II IDE to evaluate the device.</WRAP>
  
-Options:+If the nios2-terminal connected to the device the message ** AD5755 OK ** should appear at the Nios II Console.
  
-  * User Bit – This bit is mapped to Bit D11 of the status register.  +{{ :resources:fpga:altera:bemicro:nios2_console_ok.png?600 }}
-  * Software Reset – Performs a reset of the AD5755. +
  
 +By using the command **help?**, can list out all the available commands for the current device, with a small description containing indications how to use them.
  
 +{{ :resources:fpga:altera:bemicro:nios2_console_help.png?600 }}
  
-{{page>troubleshooting}}+The **AD5755** support the following commands, which can used to evaluate the **AD5755** converter:
  
 +^ **Command** ^ **Description** ^
 +| **help?** | Display all available commands |
 +| **register?** | Get register value for a specified channel, the command has two arguments: register address and channel |
 +| **register=** | Set a register value, the command has four arguments: register type, which can be data or control, register address, channel number and the desired value |
 +| **power?** | Display the power state of the dc-to-dc converters, DAC and internal amplifiers for the selected channel. The command has one argument : channel |
 +| **power=** | Set up the power state of the dc-to-dc converters, DAC and internal amplifiers for the selected channel. The command has two arguments: channel and 1 for ON and 0 for OFF |
 +| **range?** | Display the range of the selected channel. The command has one argument : channel |
 +| **range=** | Set the range of the selected channel. Has two argument: channel and range |
 +| **voltage?** | Display the output voltage of a specified channel. The command has one argument: channel |
 +| **voltage=** | Set the output voltage of a specified channel. The command using two arguments: channel and the desired value |
 +| **current?** | Display the output current of a specified channel. The command has one argument: channel |
 +| **current=** | Set the output current of a specified channel. The command using two arguments: channel and the desired value |
 +====== More information ======
 +  * [[ez>community/fpga|ask questions about the FPGA reference design]]
 +  * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
resources/fpga/altera/bemicro/ad5755.1325770500.txt.gz · Last modified: 05 Jan 2012 14:35 (external edit)

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