This lab presents the steps to setup an environment for using the EVAL-AD5668SDZ evaluation board together with the BeMicro SDK USB stick, the Nios II Embedded Development Suite (EDS) and the Micrium μC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-AD5668SDZ Evaluation Board with the BeMicro SDK Platform.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD5668SDZ Evaluation Board.
The EVAL-AD5668EBZ / AD5668SD_Z evaluation board is a member of a growing number of boards available for the SDP. Designed to help customers evaluate performance or quickly prototype new AD5668 circuits and reduce design time, the EVAL-AD5668EBZ / AD5668SD_Z evaluation board can operate from a single 2.7 V to 5.5 V supply. The part incorporates an internal 1.25 V or 2.5 V on-board reference to give an output voltage span of 2.5 V or 5 V, respectively. The on-board reference is off at power-up allowing for the use of an external reference; the REF195 is used on this evaluation board. The AD5668 must be written to after power-up to turn on the internal reference.
The AD5668 is a low power, octal, 16-bit, buffered voltage-output DAC. The device operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. The AD5668 has an on-chip reference with an internal gain of 2. The AD5668-1 has an 1.25 V 5 ppm/°C reference, giving a full-scale output range of 2.5 V; the AD5668-2, -3 has a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The AD5668 utilizes a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Below is presented the list of required hardware items:
Below is presented the list of required software tools:
The Quartus II design software and the Nios II EDS is available via the Altera Complete Design Suite DVD or by downloading from the web.
The Micrium uC/Probe Trial version 2.5 is available via download from the web at http://micrium.com/tools/ucprobe/trial/. After installation add to the “Path” system variable the entry “%QUARTUS_ROOTDIR%\bin\“ on the third position in the list.
Create a folder called “ADIEvalBoardLab” on your PC and extract the ADIEvalBoardLab.zip archive to this folder. Make sure that there are NO SPACES in the directory path. After extracting the archive the following folders should be present in the ADIEvalBoardLab folder: FPGA, Software, ucProbeInterface, NiosCpu.
After the Quartus II and Nios II software packages are installed, you can plug the BeMicro SDK board into your USB port. Your Windows PC will find the new hardware and try to install the driver.
Since Windows cannot locate the driver for the device the automatic installation will fail and the driver has to be installed manually. In the Device Manager right click on the USB-Blaster device and select Update Driver Software.
In the next dialog box select the option Browse my computer for driver software. A new dialog will open where it is possible to point to the driver’s location. Set the location to altera\<version number>\quartus\drivers\usb-blaster and press Next.
If Windows presents you with a message that the drivers have not passed Windows Logo testing, please click “Install this driver software anyway”. Upon installation completion a message will be displayed to inform that the installation is finished.
The next sections of this lab present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load into the FPGA an image that contains a fully functional system that can be used together with the uC-Probe interface for the ADI platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image run the program_fpga.bat batch file located in the ADIEvalBoardLab/FPGA folder. After the image was loaded the system must be reset. Now the FPGA contains a fully functional system and it is possible to skip directly to the DEMONSTRATION PROJECT USER INTERFACE section of this lab.
The lab is delivered together with a set of design files that are used to evaluate the ADI part. The FPGA image that must be loaded into the BeMicroSDK FPGA is included in the design files. This section presents the components included in the FPGA image and also the procedure to load the image into the FPGA.
The following components are implemented in the FPGA design:
|EPCS FLASH CONTROLLER
To load the FPGA image the following steps must be performed:
After finishing, the image is permanently loaded to the configuration Flash and the system will start with a blinking LED after reset or power up.
This section presents the steps for developing a software application that will run on the BeMicroSDK system and will be used for controlling and monitoring the operation of the ADI evaluation board.
Launch the Nios II SBT from the Start → All Programs → Altera → Nios II EDS 11.0 → Nios II 11.0 Software Build Tools for Eclipse (SBT).
NOTE: Windows 7 users will need to right-click and select Run as administrator. Another method is to right-click and select Properties and click on the Compatibility tab and select the Run This Program As An Administrator checkbox, which will make this a permanent change.
The tool will create two new software project directories. Each Nios II application has 2 project directories in the Eclipse workspace.
Since you chose the blank project template, there are no source files in the application project directory at this time. The BSP contains a directory of software drivers as well as a system.h header file, system initialization source code and other software infrastructure.
The software project provided in this lab does not make use of an operating system. All stdout, stdin and stderr messages will be directed to the jtag_uart.
In addition to the board support package settings configured using the BSP Editor, there are other compilation settings managed by the Eclipse environment such as compiler flags and optimization level.
In Windows Explorer locate the project directory which contains a directory called Software. In Windows Explorer select all the files and directories from the Software folder and drag and drop them into the Eclipse software project ADIEvalBoard.
Just as you configured the optimization level for the BSP project, you should set the optimization level for the application software project ADIEvalBoard as well.
Application code can be conveniently organized in a directory structure. This section shows how to define these paths in the makefile.
These 2 steps will compile and build the associated board support package, then the actual application software project itself. The result of the compilation process will be an Executable and Linked Format (.elf) file for the application, the ADIEvalBoard.elf file.
The BeMicroSDK hardware is designed with a System ID peripheral. This peripheral is assigned a unique value based on when the hardware design was last modified in the SOPC Builder tool. SOPC Builder also places this information in the .sopcinfo hardware description file. The BSP is built based on the information in the .sopcinfo file.
To run the software project on the Nios II processor:
This will re-build the software project to create an up–to-date executable and then download the code into memory on the BeMicroSDK hardware. The debugger resets the Nios II processor, and it executes the downloaded code. Note that the code is verified in memory before it is executed.
The code size and start address might be different than the ones displayed in the above screenshot.
A notable challenge in embedded systems development is to overcome the lack of feedback that such systems typically provide. Many developers resort to blinking LEDs or instrumenting their code with printf() in order to determine whether or not their systems are running as expected. Micrium provides a unique tool named µC-Probe to assist these developers. With this tool, developers can effortlessly read and write the variables on a running embedded system. This section presents the steps required to install the Micrium uC-Probe software tool and to run the demonstration project for the ADI evaluation board. A description of the uC-Probe demonstration interface is provided.
Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.
Select uC-Probe options.
Set target board communication protocol as JTAG UART
Setup JTAG UART communication settings
The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD5668EBZ / AD5668SD_Z evaluation board.
Section A is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems.
Section B is used to set the output value on the DAC channels. In order to use this functionality, one should select the channel, select the data bits and press the Set on DAC switch. If the LED is active, the value will be continuously updated on the DAC. The DAC may have different reference voltages, so the user should select the value of the reference currently used. Based on this voltage, the output voltage corresponding to the data bits will be displayed.
Section C is used to send any command to the AD5668. The command list is available in table “Command Definitions” from the datasheet. Using the sliders, the command, address and databits to be sent should be configured. After that, Send command to DAC switch should be activated. There are two sliders used for setting the Value, one for large values and one for small values.
For command 4, Power down/power up DAC, the Channel value is used to select the power down mode: 0 for normal operation, 1 for 1k to GND, 2 for 100k to GND and 3 for Three-state operation. The least significant eight bits from the Value are used for channel selection. For additional information see datasheet .
For command 5, Load clear code register, the last two bits from value parameter are used as Clear code register bits. 0 will load the clear registers with 0x0000, 1 will load them with 0x8000, 2 will load them with 0xFFFF and 3 is used for no operation.
For command 6, Load LDAC register, the least significant eight bits from the value are used for channel selection. If 1, the channel will consider always the LDAC active.
For command 7, Reset, the value and channel parameters are not important.
For command 8, Set up internal REF register, the last bit from Value is used for reference selection (0 internal reference off, other than 0 internal reference on).
Section D is used to toggle the hardware pins. The functionality of the pins is described in the datasheet, table “Pin Function Descriptions”. When pressing the Toggle \LDAC switch, a HIGH to LOW and a LOW to HIGH transition will be initiated on the LDAC pin. The DAC registers will be updated with the input registers data. When pressing the Toggle \CLR switch, a HIGH to LOW and a LOW to HIGH transition will be initiated on the CLR pin. This will update the Input registers and DAC registers with the data contained in the CLR code register: zero, midscale or full scale. Default settings clear the output to 0.
Section E is used to for configuring the ADC. It is possible that the ADC to be supplied with a different voltage than the reference voltage used for the DAC case in which ADC Supply should be correctly configured by the user. Activating the Continuous loop button, the ADC will read continuously sequentially all eight channels from the DAC. If it is not active, the ADC will only read the channel selected in section B. The voltage is computed based on the ADC Supply configuration.
In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: